Abstract—Within-die parameter variation poses a major challenge to high-performance microprocessor design, negatively impacting a processor’s frequency and leakage power. Addressing this problem, this paper proposes a microarchitecture-aware model for process variation—including both random and systematic effects. The model is specified using a small number of highly intuitive parameters. Using the variation model, this paper also proposes a framework to model timing errors caused by parameter variation. The model yields the failure rate of microarchitectural blocks as a function of clock frequency and the amount of variation. With the combination of the variation model and the error model, we have VARIUS, a comprehensive model that is capable of producing detailed statistics of timing errors as a function of different process parameters and operating conditions. We propose possible applications of VARIUS to microarchitectural research. I.

Multi-core architectures introduce a new granularity at which process variations may occur, yielding asymmetry among cores that were designed—and that software expects—to be symmetric in performance. The chief source of this phenomenon are highly correlated, “systematic” within-die variations such as optical imperfections yielding variations across the exposure field. Per-core voltages can be used to bring all cores to the same performance level, but this compensation strategy also affects power, chiefly due to leakage power. Boosting a core’s frequency may therefore boost its leakage sufficiently to engage thermal throttling. This sets up a tradeoff between static performance asymmetry due to frequency variation versus dynamic performance asymmetry due to thermal throttling. This paper explores the potential magnitude of these effects.

In this paper, we approach the gate sizing problem in VLSI circuits in the context of increasing variability of process and circuit parameters as technology scales into the nanometer regime. We present a statistical sizing approach that takes into account randomness in gate delays by formulating a robust linear program that can be solved efficiently. We demonstrate the efficiency and computational tractability of the proposed algorithm on the various ISCAS’85 benchmark circuits. Across the benchmarks, compared to the deterministic approach, the power savings range from 23 − 30 % for the same timing target and the yield level, the average power saving being 28%. The runtime is reasonable, ranging from a few seconds to around 10 mins, and grows linearly.

Parameter variation is detrimental to a processor’s frequency and leakage power. One proposed technique to mitigate it is Fine-Grain Body Biasing (FGBB), where different parts of the processor chip are given a voltage bias that changes the speed and leakage properties of their transistors. This technique has been proposed for static application, with the bias voltages being programmed at manufacturing time for worst-case conditions. In this paper, we introduce Dynamic FGBB (D-FGBB), which allows the continuous re-evaluation of the bias voltages to adapt to dynamic conditions. Our results show that D-FGBB is very versatile and effective. Specifically, with the processor working in normal mode at fixed frequency, D-FGBB reduces the leakage power of the chip by an average of 28–42 % compared to static FGBB. Alternatively, with the processor working in a high-performance mode, D-FGBB increases the processor frequency by an average of 7–9 % compared to static FGBB — or 7–16 % compared to no body biasing. Finally, we also show that D-FGBB can be synergistically combined with Dynamic Voltage and Frequency Scaling (DVFS), creating an effective means to manage power. 1.

In this paper we propose a novel parameterized interconnect order reduction algorithm, CORE, to efficiently capture both inter-die and intra-die variations. CORE applies a two-step explicit-and-implicit scheme for multi-parameter moment matching. As such, CORE can match significantly more moments than other traditional techniques using the same model size. In addition, a recursive Arnoldi algorithm is proposed to quickly construct the Krylov subspace that is required for parameterized order reduction. Applying the recursive Arnoldi algorithm significantly reduces the computation cost for model generation. Several RC and RLC interconnect examples demonstrate that CORE can provide up to 10x better modeling accuracy than other traditional techniques, while achieving smaller model complexity (i.e. size). It follows that these interconnect models generated by CORE can provide more accurate simulation result with cheaper simulation cost, when they are utilized for gate-interconnect cosimulation. 1.

Large-scale process fluctuations in nano-scale IC technologies suggest applying high-order (e.g., quadratic) response surface models to capture the circuit performance variations. Fitting such models requires significantly more simulation samples and solving much larger linear equations. In this paper, we propose a novel projection-based extraction approach, PROBE, to efficiently create quadratic response surface models and capture both interdie and intra-die variations with affordable computation cost. PROBE applies a novel projection scheme to reduce the response surface modeling cost (i.e., both the required number of samples and the linear equation size) and make the modeling problem tractable even for large problem sizes. In addition, a new implicit power iteration algorithm is developed to find the optimal projection space and solve for the unknown model coefficients. Several circuit examples from both digital and analog circuit modeling applications demonstrate that PROBE can generate accurate response surface models while achieving up to 12x speedup compared with the traditional methods. 1.

A deterministic activity network (DAN) is a collection of activities, each with some duration, along with a set of precedence constraints, which specify that activities begin only when certain others have finished. One critical performance measure for an activity network is its makespan, which is the minimum time required to complete all activities. In a stochastic activity network (SAN), the durations of the activities and the makespan are random variables. The analysis of SANs is quite involved, but can be carried out numerically by Monte Carlo analysis. This paper concerns the optimization of a SAN, i.e., the choice of some design variables that affect the probability distributions of the activity durations. We concentrate on the problem of minimizing a quantile (e.g., 95%) of the makespan, subject to constraints on the variables. This problem has many applications, ranging from project management to digital integrated circuit (IC) sizing (the latter being our motivation). While there are effective methods for optimizing DANs, the SAN optimization problem is much more difficult; the few existing methods cannot handle large-scale problems.

As VLSI technology continues to scale, parameter variation is about to pose a major challenge to high-performance processor design. In particular, within-die variation is directly detrimental to a processor’s frequency and leakage power. To gain an understanding of this problem, this paper starts out by proposing a microarchitecture-aware model for parameter variation. It includes both random and systematic effects. It is partially calibrated with empirical data and uses a few intuitive parameters. Then, we extend the framework to model timing errors caused by parameter variation. This model yields the failure rate of microarchitectural blocks as a function of frequency and the amount of variation. With the combination of the variation model and the error model, we have VARIUS, a comprehensive model that is capable of producing detailed statistics of timing errors as a function of different process parameters and operating conditions. We propose possible applications of VAR-IUS to microarchitectural research. 1.

Process variability in deeply scaled CMOS has both random and systematic components, with a varying degree of spatial correlation. A test chip has been built to study the effects of circuit layout on variability of delay and power dissipation in 90nm CMOS. The delay is characterized through the spread of ring oscillator frequencies and the transistor leakage is measured by using an on-chip ADC. 1.

This paper develops a new model of parameter variations for use in early-stage, pre-RTL architecture studies. It improves over prior models by extending the FMAX model to more faithfully model various microarchitecture structures, especially SRAM, which is dominant in contemporary superscalar processors. It also incorporates optical phenomena, which show strong spatial correlation but nevertheless cannot be ignored for large dies. Finally, it incorporates IR Vdd drop and temperature, and closes all these feedback loops to obtain converged estimates of frequency, leakage, voltage, and temperature. With this model, we explore PVT limitations on multi-core integration and the difficulties in obtaining matched cores.