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15
Symbolic Boolean manipulation with ordered binarydecision diagrams
 ACM Computing Surveys
, 1992
"... Ordered BinaryDecision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as grap ..."
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Cited by 879 (11 self)
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Ordered BinaryDecision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as graph algorithms on OBDD
Checking equivalence for partial implementations
 UNIVERSITY OF COLORADO AT BOULDER
, 2001
"... We consider the problem of checking whether a partial implementation can (still) beextended to a complete design which is equivalent to a given full specification. Several algorithms trading off accuracy and computational resources are presented:Starting with a simple 0,1,Xbased simulation, which a ..."
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Cited by 28 (12 self)
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We consider the problem of checking whether a partial implementation can (still) beextended to a complete design which is equivalent to a given full specification. Several algorithms trading off accuracy and computational resources are presented:Starting with a simple 0,1,Xbased simulation, which allows approximate solutions, but is not able to find all errors in the partial implementation, we consider more and more exactmethods finally covering all errors detectable in the partial implementation. The exact algorithm reports no error if and only if the current partial implementation conforms tothe specification, i.e. it can be extended to a full implementation which is equivalent to the specification.We give a series of experimental results demonstrating the effectiveness and feasibility of the methods presented.
Functional Simulation using Binary Decision Diagrams
 In Int'l Conf. on CAD
, 1997
"... In many verification techniques fast functional evaluation of a Boolean network is needed. We investigate the idea of using Binary Decision Diagrams (BDDs) for functional simulation. The areatime tradeoff that results from different minimization techniques of the BDD is discussed. We propose new m ..."
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Cited by 22 (4 self)
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In many verification techniques fast functional evaluation of a Boolean network is needed. We investigate the idea of using Binary Decision Diagrams (BDDs) for functional simulation. The areatime tradeoff that results from different minimization techniques of the BDD is discussed. We propose new minimization methods based on dynamic reordering that allow smaller representations with (nearly) no runtime penalty.
Multilevel Synthesis for Safe Replaceability
 in Proc. Intl. Conf. on ComputerAided Design
, 1994
"... We describe the condition that a sequential digital design is a safe replacement for an existing design without making any assumptions about a known initial state of the design or about its environment. We formulate a safe replacement condition which guarantees that if an original design is replaced ..."
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Cited by 14 (4 self)
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We describe the condition that a sequential digital design is a safe replacement for an existing design without making any assumptions about a known initial state of the design or about its environment. We formulate a safe replacement condition which guarantees that if an original design is replaced by a new design, the interacting environment cannot detect the change by observing the inputoutput behavior of the new design; conversely, if a replacement design does not satisfy our condition an environment can potentially detect the replacement (in this sense the replacement is potentially unsafe). Our condition allows simplification of the state transition diagram of an original design. We use the safe replacement condition to derive a sequential resynthesis method for area reduction of gatelevel designs. We have implemented our resynthesis algorithm and we report experimental results. 1
An introduction to zerosuppressed binary decision diagrams
 in ‘Proceedings of the 12th Symposium on the Integration of Symbolic Computation and Mechanized Reasoning
, 2001
"... ..."
Compact SOP Representations for MultipleOutput Functions  An Encoding Method using MultipleValued Logic 
, 2001
"... This paper shows a method to represent a multipleoutput function: Encoded characteristic function for nonzero outputs (ECFN). The ECFN uses (n + u) binary variables to represent an ninput moutput function, where u = dlog 2 me. The size of the sumofproducts expressions (SOPs) depends on the enc ..."
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Cited by 9 (8 self)
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This paper shows a method to represent a multipleoutput function: Encoded characteristic function for nonzero outputs (ECFN). The ECFN uses (n + u) binary variables to represent an ninput moutput function, where u = dlog 2 me. The size of the sumofproducts expressions (SOPs) depends on the encoding method of the outputs. For some class of functions, the optimal encoding produces SOPs with O(n) products, while the worst encoding produces SOPs with O(2 n ) products. We formulate encoding problem and show a heuristic optimization method. Experimental results using standard benchmark functions show the usefulness of the method. Index term: Multipleoutput function, encoding problem, multiplevalued logic, TDM, SOP, characteristic function. 1.
Rectification Method for LookupTable Type FPGA's
 In Proc. of ICCAD92
, 1992
"... Field programmable gate array (FPGA) makes rapid prototyping an easier task, and is useful in many applications due to its growing speed and capacity. In this paper, we present a rectification method for lookup table type FPGA's. Instead of changing the netlist of a circuit, we only modify function ..."
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Cited by 9 (2 self)
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Field programmable gate array (FPGA) makes rapid prototyping an easier task, and is useful in many applications due to its growing speed and capacity. In this paper, we present a rectification method for lookup table type FPGA's. Instead of changing the netlist of a circuit, we only modify functionality realized by lookup tables and keep the netlist equal so that there will be no change on the delay of the circuit. We formalize the problem using characteristic functions and present a redesign method based on Boolean relation techniques. 1 Introduction Field Programmable Gate Array (FPGA) is an important technology which has recently attracted much attention due to its advantage of rapid prototyping. There has also been increasing interest in using FPGA's for lowvolume production of ASIC designs. Not a few papers have been published so far on logic synthesis for FPGA's, for example, Chortle and its successors Chortlecrf and Chortled by Francis et al. [10, 9, 11], DAGmap by Cong ...
Exact Required Time Analysis via False Path Detection
 IN PROCEEDINGS OF 34TH ACM/IEEE DESIGN AUTOMATION CONFERENCE
, 1997
"... This paper addresses how to compute required times at intermediate nodes in a combinational network given required times at primary outputs. The simplest approach is to compute them based on topological delay analysis without any consideration of false paths. In this paper, however, we take into acc ..."
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Cited by 8 (6 self)
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This paper addresses how to compute required times at intermediate nodes in a combinational network given required times at primary outputs. The simplest approach is to compute them based on topological delay analysis without any consideration of false paths. In this paper, however, we take into account false paths between the intermediate nodes and the primary outputs explicitly to characterize the timing constraints at the nodes more accurately. We show that this approach leads to a technique for computing a more refined and relaxed timing constraint than that obtained by topological analysis. We generalize the notion of required times from a single constant to a relation where a signal is required at different times depending on the values of the other signals.
Synthesizing Interacting Finite State Machines
 In Proceedings of the International Conference on Computer Design
, 1994
"... We present a mathematical framework for analyzing the synthesis of interacting finite state systems. The logic S1S is used to derive simple, rigorous, and constructive solutions to problems in sequential synthesis. We obtain exact and approximate sets of permissible FSM network behavior, and address ..."
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Cited by 6 (5 self)
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We present a mathematical framework for analyzing the synthesis of interacting finite state systems. The logic S1S is used to derive simple, rigorous, and constructive solutions to problems in sequential synthesis. We obtain exact and approximate sets of permissible FSM network behavior, and address the issue of FSM realizability. This approach is also applied to synthesizing systems with fairness and timed systems. 1 Introduction The advent of modern VLSI CAD tools has radically changed the process of designing digital systems. The first CAD tools automated the final stages of design, such as placement and routing. As the low level steps became better understood, the focus shifted to the higher stages. In particular logic synthesis, the science of optimizing designs (for various measures such as area, speed, or power) specified at the gate level, has shifted to the forefront of CAD research. Another area rapidly gaining importance is design verification, the study of systematic metho...
Sequential synthesis by language equation solving
 In The Proceedings of the International Workshop on Logic Synthesis
, 2003
"... Consider the problem of designing a component that combined with a known part of a system, called the context, conforms to a given overall specification. This question arises in several applications ranging from logic synthesis to the design of discrete controllers. We cast the problem as solving ab ..."
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Cited by 6 (5 self)
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Consider the problem of designing a component that combined with a known part of a system, called the context, conforms to a given overall specification. This question arises in several applications ranging from logic synthesis to the design of discrete controllers. We cast the problem as solving abstract equations over languages and study the most general solutions under the synchronous and parallel composition operators. We also specialize such language equations to languages associated with important classes of automata used for modeling systems, e.g., regular languages as counterparts of finite automata, FSM languages as counterparts of FSMs. Thus we can operate algorithmically on those languages through their automata and study how to solve effectively their language equations. We investigate the maximal subsets of solutions closed with respect to various language properties. In particular, we investigate classes of the largest compositional solutions (defined by properties exhibited by the composition of the solution and of the context). We provide the first algorithm to compute the largest compositionally progressive solution of synchronous equations. This approach unifies in a seamless frame previously reported techniques. As an application we solve the classical problem of synthesizing a converter between a mismatched pair of protocols, using their specifications, as well as those of the channel and of the required service. 1