Results 1  10
of
21
Symbolic Boolean manipulation with ordered binarydecision diagrams
 ACM Computing Surveys
, 1992
"... Ordered BinaryDecision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as grap ..."
Abstract

Cited by 942 (14 self)
 Add to MetaCart
Ordered BinaryDecision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as graph algorithms on OBDD
Fast functional simulation using branching programs
 In Proceedings of the IEEE International Conference on ComputerAided Design
, 1995
"... This paper addresses the problem of speeding up functional (delayindependent) logic simulation for synchronous digital systems. The problem needs very little new motivation – cyclebased functional simulation is the largest consumer of computing cycles in system design. Most existing simulators for ..."
Abstract

Cited by 64 (0 self)
 Add to MetaCart
(Show Context)
This paper addresses the problem of speeding up functional (delayindependent) logic simulation for synchronous digital systems. The problem needs very little new motivation – cyclebased functional simulation is the largest consumer of computing cycles in system design. Most existing simulators for this task can be classified as being either event driven or levelized compiledcode, with the levelized compiled code simulators generally being considered faster for this task. An alternative technique, based on evaluation using branching programs, was suggested about a decade ago in the context of switch level functional simulation. However, this had very limited application since it could not handle the large circuits encountered in practice. This paper resurrects the basic idea present this technique and provides significant modifications that enable its application to contemporary industrial strength circuits. We present experimental results that demonstrate up to a 10X speedup over levelized compiled code simulation for a large suite of benchmark circuits as well as for industrial examples with over 40,000 gates. 1
Checking equivalence for partial implementations
 UNIVERSITY OF COLORADO AT BOULDER
, 2001
"... We consider the problem of checking whether a partial implementation can (still) beextended to a complete design which is equivalent to a given full specification. Several algorithms trading off accuracy and computational resources are presented:Starting with a simple 0,1,Xbased simulation, which a ..."
Abstract

Cited by 32 (12 self)
 Add to MetaCart
(Show Context)
We consider the problem of checking whether a partial implementation can (still) beextended to a complete design which is equivalent to a given full specification. Several algorithms trading off accuracy and computational resources are presented:Starting with a simple 0,1,Xbased simulation, which allows approximate solutions, but is not able to find all errors in the partial implementation, we consider more and more exactmethods finally covering all errors detectable in the partial implementation. The exact algorithm reports no error if and only if the current partial implementation conforms tothe specification, i.e. it can be extended to a full implementation which is equivalent to the specification.We give a series of experimental results demonstrating the effectiveness and feasibility of the methods presented.
Functional Simulation using Binary Decision Diagrams
 In Int'l Conf. on CAD
, 1997
"... In many verification techniques fast functional evaluation of a Boolean network is needed. We investigate the idea of using Binary Decision Diagrams (BDDs) for functional simulation. The areatime tradeoff that results from different minimization techniques of the BDD is discussed. We propose new m ..."
Abstract

Cited by 25 (4 self)
 Add to MetaCart
(Show Context)
In many verification techniques fast functional evaluation of a Boolean network is needed. We investigate the idea of using Binary Decision Diagrams (BDDs) for functional simulation. The areatime tradeoff that results from different minimization techniques of the BDD is discussed. We propose new minimization methods based on dynamic reordering that allow smaller representations with (nearly) no runtime penalty.
Constructive multilevel synthesis by way of functional properties
 Ph.D. dissertation, Comput. Sci. Eng., Univ. Michigan, Ann Arbor
, 2001
"... ii ..."
(Show Context)
Multilevel Synthesis for Safe Replaceability
 in Proc. Intl. Conf. on ComputerAided Design
, 1994
"... We describe the condition that a sequential digital design is a safe replacement for an existing design without making any assumptions about a known initial state of the design or about its environment. We formulate a safe replacement condition which guarantees that if an original design is replaced ..."
Abstract

Cited by 13 (4 self)
 Add to MetaCart
(Show Context)
We describe the condition that a sequential digital design is a safe replacement for an existing design without making any assumptions about a known initial state of the design or about its environment. We formulate a safe replacement condition which guarantees that if an original design is replaced by a new design, the interacting environment cannot detect the change by observing the inputoutput behavior of the new design; conversely, if a replacement design does not satisfy our condition an environment can potentially detect the replacement (in this sense the replacement is potentially unsafe). Our condition allows simplification of the state transition diagram of an original design. We use the safe replacement condition to derive a sequential resynthesis method for area reduction of gatelevel designs. We have implemented our resynthesis algorithm and we report experimental results. 1
Rectification Method for LookupTable Type FPGA's
 In Proc. of ICCAD92
, 1992
"... Field programmable gate array (FPGA) makes rapid prototyping an easier task, and is useful in many applications due to its growing speed and capacity. In this paper, we present a rectification method for lookup table type FPGA's. Instead of changing the netlist of a circuit, we only modify fun ..."
Abstract

Cited by 10 (2 self)
 Add to MetaCart
(Show Context)
Field programmable gate array (FPGA) makes rapid prototyping an easier task, and is useful in many applications due to its growing speed and capacity. In this paper, we present a rectification method for lookup table type FPGA's. Instead of changing the netlist of a circuit, we only modify functionality realized by lookup tables and keep the netlist equal so that there will be no change on the delay of the circuit. We formalize the problem using characteristic functions and present a redesign method based on Boolean relation techniques. 1 Introduction Field Programmable Gate Array (FPGA) is an important technology which has recently attracted much attention due to its advantage of rapid prototyping. There has also been increasing interest in using FPGA's for lowvolume production of ASIC designs. Not a few papers have been published so far on logic synthesis for FPGA's, for example, Chortle and its successors Chortlecrf and Chortled by Francis et al. [10, 9, 11], DAGmap by Cong ...
An Introduction to ZeroSuppressed Binary Decision Diagrams. http://www.ee.pdx.edu/~alanmi/research
, 2001
"... ..."
(Show Context)
Compact SOP Representations for MultipleOutput Functions  An Encoding Method using MultipleValued Logic 
, 2001
"... This paper shows a method to represent a multipleoutput function: Encoded characteristic function for nonzero outputs (ECFN). The ECFN uses (n + u) binary variables to represent an ninput moutput function, where u = dlog 2 me. The size of the sumofproducts expressions (SOPs) depends on the enc ..."
Abstract

Cited by 9 (8 self)
 Add to MetaCart
This paper shows a method to represent a multipleoutput function: Encoded characteristic function for nonzero outputs (ECFN). The ECFN uses (n + u) binary variables to represent an ninput moutput function, where u = dlog 2 me. The size of the sumofproducts expressions (SOPs) depends on the encoding method of the outputs. For some class of functions, the optimal encoding produces SOPs with O(n) products, while the worst encoding produces SOPs with O(2 n ) products. We formulate encoding problem and show a heuristic optimization method. Experimental results using standard benchmark functions show the usefulness of the method. Index term: Multipleoutput function, encoding problem, multiplevalued logic, TDM, SOP, characteristic function. 1.
Exact Required Time Analysis via False Path Detection
 IN PROCEEDINGS OF 34TH ACM/IEEE DESIGN AUTOMATION CONFERENCE
, 1997
"... This paper addresses how to compute required times at intermediate nodes in a combinational network given required times at primary outputs. The simplest approach is to compute them based on topological delay analysis without any consideration of false paths. In this paper, however, we take into acc ..."
Abstract

Cited by 8 (6 self)
 Add to MetaCart
(Show Context)
This paper addresses how to compute required times at intermediate nodes in a combinational network given required times at primary outputs. The simplest approach is to compute them based on topological delay analysis without any consideration of false paths. In this paper, however, we take into account false paths between the intermediate nodes and the primary outputs explicitly to characterize the timing constraints at the nodes more accurately. We show that this approach leads to a technique for computing a more refined and relaxed timing constraint than that obtained by topological analysis. We generalize the notion of required times from a single constant to a relation where a signal is required at different times depending on the values of the other signals.