Results 1  10
of
34
Symbolic Boolean manipulation with ordered binarydecision diagrams
 ACM Computing Surveys
, 1992
"... Ordered BinaryDecision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as grap ..."
Abstract

Cited by 942 (14 self)
 Add to MetaCart
Ordered BinaryDecision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as graph algorithms on OBDD
Symbolic model checking for sequential circuit verification
 IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
, 1994
"... The temporal logic model checking algorithm of Clarke, Emerson, and Sistla [17] is modified to represent state graphs using binary decision diagrams (BDD’s) [7] and partitioned trunsirion relations [lo], 1111. Because this representation captures some of the regularity in the state space of circuit ..."
Abstract

Cited by 239 (11 self)
 Add to MetaCart
(Show Context)
The temporal logic model checking algorithm of Clarke, Emerson, and Sistla [17] is modified to represent state graphs using binary decision diagrams (BDD’s) [7] and partitioned trunsirion relations [lo], 1111. Because this representation captures some of the regularity in the state space of circuits with data path logic, we are able to verify circuits with an extremely large number of states. We demonstrate this new technique on a synchronous pipelined design with approximately 5 x 10^120 states. Our model checking algorithm handles full CTL with fairness constraints. Consequently, we are able to express a number of important liveness and fairness properties, which would otherwise not be expressible in CTL. We give empirical results on the performance of the algorithm applied to both synchronous and asynchronous circuits with data path logic.
Retiming and resynthesis: A complexity perspective
 IEEE TCAD
, 2006
"... Abstract—Transformations using retiming and resynthesis operations are the most important and practical (if not the only) techniques used in optimizing synchronous hardware systems. Although these transformations have been studied extensively for over a decade, questions about their optimization cap ..."
Abstract

Cited by 17 (5 self)
 Add to MetaCart
(Show Context)
Abstract—Transformations using retiming and resynthesis operations are the most important and practical (if not the only) techniques used in optimizing synchronous hardware systems. Although these transformations have been studied extensively for over a decade, questions about their optimization capability and verification complexity are not answered fully. Resolving these questions may be crucial in developing more effective synthesis and verification algorithms. This paper settles the above two open problems. The optimization potential is resolved through a constructive algorithm which determines if two given finite state machines (FSMs) are transformable to each other via retiming and resynthesis operations. Verifying the equivalence of two FSMs under such transformations, when the history of iterative transformation is unknown, is proved to be polynomialspacecomplete and hence just as hard as general equivalence checking, contrary to a common belief. As a result, we advocate a conservative design methodology for the optimization of synchronous hardware systems to ameliorate verifiability. Our analysis reveals some properties about initializing FSMs transformed under retiming and resynthesis. On the positive side, a lagindependent bound is established on the length increase of initialization sequences for FSMs under retiming. It allows a simpler incremental construction of initialization sequences compared to prior approaches. On the negative side, we show that there is no analogous transformationindependent bound when resynthesis and retiming are iterated. Nonetheless, an algorithm computing the exact length increase is presented. Index Terms—Computational complexity, equivalence verification, finite state machine (FSM), initialization sequence, resynthesis, retiming. I.
Symbolic Computation of the Valid States of a Sequential Machine: Algorithms and Discussion
 In International workshop on formal methods for correct VLSI design
, 1991
"... Computing the valid states of a sequential machine is a problem that appears in several verification and synthesis processes. The computation of the image of a vectorial function is the main operation required to solve this problem. The aim of this paper is to show how the image computation can ..."
Abstract

Cited by 17 (0 self)
 Add to MetaCart
(Show Context)
Computing the valid states of a sequential machine is a problem that appears in several verification and synthesis processes. The computation of the image of a vectorial function is the main operation required to solve this problem. The aim of this paper is to show how the image computation can be symbolically performed, and to discuss the complexities and behaviors of several approaches. We propose a parametric algorithm that performs the image computation. Several instances of this algorithm can be obtained according to the results and the heuristics we give to analyze and to improve the computation. Two instances of this algorithm will be compared on practical examples. 1 Introduction The valid states of a sequential machine are needed in several verification and synthesis problems: comparing uncompletely defined Mealy machines [7, 8, 12, 13, 16], finding minimal differentiating input sequences, automatic test pattern generation [7], minimal reset sequences generation [1...
Identifying sequentially untestable faults using illegal states
 Proc. of 13th IEEE VLSI Test Symposium
, 1995
"... ..."
(Show Context)
Multilevel Synthesis for Safe Replaceability
 in Proc. Intl. Conf. on ComputerAided Design
, 1994
"... We describe the condition that a sequential digital design is a safe replacement for an existing design without making any assumptions about a known initial state of the design or about its environment. We formulate a safe replacement condition which guarantees that if an original design is replaced ..."
Abstract

Cited by 13 (4 self)
 Add to MetaCart
(Show Context)
We describe the condition that a sequential digital design is a safe replacement for an existing design without making any assumptions about a known initial state of the design or about its environment. We formulate a safe replacement condition which guarantees that if an original design is replaced by a new design, the interacting environment cannot detect the change by observing the inputoutput behavior of the new design; conversely, if a replacement design does not satisfy our condition an environment can potentially detect the replacement (in this sense the replacement is potentially unsafe). Our condition allows simplification of the state transition diagram of an original design. We use the safe replacement condition to derive a sequential resynthesis method for area reduction of gatelevel designs. We have implemented our resynthesis algorithm and we report experimental results. 1
Abstract interpretation using typed decision graphs
 Science of Computer Programming
, 1998
"... Abstract. This article presents a way of implementing abstract interpretations that can be very efficient. The improvement lies in the use of a symbolic representation of boolean functions called Typed Decision Graphs (TDGs), a refinement of Binary Decision Diagrams. A general procedure for using th ..."
Abstract

Cited by 13 (5 self)
 Add to MetaCart
(Show Context)
Abstract. This article presents a way of implementing abstract interpretations that can be very efficient. The improvement lies in the use of a symbolic representation of boolean functions called Typed Decision Graphs (TDGs), a refinement of Binary Decision Diagrams. A general procedure for using this representation in abstract interpretation is given; we examine in particular the possibility of encoding higher order functions into TDGs. Moreover, this representation is used to design a widening operator based on the size of the objects represented, so that abstract interpretations will not fail due to insufficient memory. This approach is illustrated on strictness analysis of higherorder functions, showing a great increase in efficiency. 1
On the Verification of Sequential Equivalence
 IEEE Transactions on ComputerAided Design
, 2003
"... Abstract — The state explosion problem limits formal verification to small or mediumsized sequential circuits partly because BDD sizes heavily depend on the number of variables dealt with. In the worst case, a BDD size grows exponentially with the number of variables. Thus reducing this number can ..."
Abstract

Cited by 11 (3 self)
 Add to MetaCart
(Show Context)
Abstract — The state explosion problem limits formal verification to small or mediumsized sequential circuits partly because BDD sizes heavily depend on the number of variables dealt with. In the worst case, a BDD size grows exponentially with the number of variables. Thus reducing this number can possibly increase the verification capacity. In particular, this paper shows how sequential equivalence checking can be done in the sum state space. Given two finite state machines and with numbers of state variables and respectively, conventional formal methods verify equivalence by traversing the state space of the product machine, with registers. In contrast, this paper introduces a different possibility, based on partitioning the state space defined by a multiplexed machine, which can have merely registers. This substantial reduction in state variables potentially enables the verification of larger instances. Experimental results show the approach can verify benchmarks with up to registers, including all of the control outputs of microprocessor 8085. I.
Least Fixpoint Approximations for Reachability Analysis
 In Proceedings of the International Conference on ComputerAided Design
, 1999
"... The knowledge of the reachable states of a sequential circuit can dramatically speed up optimization and model checking. However, since exact reachability analysis may be intractable, approximate techniques are often preferable. Cho et al. presented the MachineByMachine (MBM) and FrameByFrame ( ..."
Abstract

Cited by 11 (4 self)
 Add to MetaCart
(Show Context)
The knowledge of the reachable states of a sequential circuit can dramatically speed up optimization and model checking. However, since exact reachability analysis may be intractable, approximate techniques are often preferable. Cho et al. presented the MachineByMachine (MBM) and FrameByFrame (FBF) methods to perform approximate FSM traversal. FBF produces tighter upper bounds than MBM; however, it usually takes much more time and it may have convergence problems. In this paper, we show that there exists a class of methodsLeast Fixpoint Approximations that compute the same results as RFBF (Reached FBF, one of the FBF methods). We show that one member of this class, which we call Least fixpoint MBM (LMBM), is as efficient as MBM, but provably more accurate. Therefore, the tradeoff that existed between MBM and RFBF has been eliminated. LMBM can compute RFBFquality approximations for all the large ISCAS89 benchmark circuits in a total of less than 9000 seconds. 1 Introduction...
How Powerful is Retiming?
, 1998
"... This paper is about exploring the power of retiming and resynthesis. We show that there exists a pair of "sequentially equivalent" designs so that one cannot be obtained from another by a sequence of retiming and resynthesis operations; the notion of sequential equivalence itself is predic ..."
Abstract

Cited by 8 (3 self)
 Add to MetaCart
This paper is about exploring the power of retiming and resynthesis. We show that there exists a pair of "sequentially equivalent" designs so that one cannot be obtained from another by a sequence of retiming and resynthesis operations; the notion of sequential equivalence itself is predicated on whether or not the designs are associated with designated initial states. Categorizing the power of retiming and resynthesis operations is closely related to the problem of verifying sequential equivalence. We show the complexity results for the sequential verification problem. However, our primary goal, namely determining sharp bounds on the power of retiming and resynthesis, and determining the complexity of the associated verification problem remains open, and we would like to present that as a challenge to the community. 1 Introduction The advent of modern VLSI CAD tools has radically changed the process of designing digital systems. The first CAD tools automated the final stages of desig...