Analog Viterbi decoders are finding widespread use in class-IV partial-response disk-drive applications. These analog realizations are often used because they are smaller and consume less power than their digital counterparts. However, class-IV signaling allows simplifications during Viterbi detection and thus existing analog decoders have limited applications. The purpose of this paper is to develop efficient analog circuits that can be used for general Viterbi detection. To demonstrate the feasibility of the proposed approach, the analog portions of two analog Viterbi decoders were fabricated in a 0.8-m BiCMOS process. With an off-chip digital path memory, operation up to 50 Mb/s is demonstrated. However, simulations indicate that with on-chip digital path memory, speeds on the order of 300 Mb/s can be achieved. The power consumption of the proposed approach is estimated to be 15 mW/state drawn from a single 5-V power supply. Index Terms---Analog, BiCMOS, communications, Viterbi. I...

In 1948 Shannon developed fundamental limits on the efficiency of communication over noisy channels. The coding theorem asserts that there are block codes with code rates arbitrarily close to channel capacity and probabilities of error arbitrarily close to zero. Fifty years later, codes for the Gaussian channel have been discovered that come close to these fundamental limits. There is now a substantial algebraic theory of error-correcting codes with as many connections to mathematics as to engineering practice, and the last 20 years have seen the construction of algebraic-geometry codes that can be encoded and decoded in polynomial time, and that beat the Gilbert–Varshamov bound. Given the size of coding theory as a subject, this review is of necessity a personal perspective, and the focus is reliable communication, and not source coding or cryptography. The emphasis is on connecting coding theories for Hamming and Euclidean space and on future challenges, specifically in data networking, wireless communication, and quantum information theory.

Abstract—Differential signaling is often used for digital chip-to-chip interconnects because it provides common-mode noise rejection. Unfortunately, differential signals generally require 2 signal paths to communicate signals. In this paper, a method for differential signaling is described that requires as few as C1 signal paths for signals. Using this method, the signal values appear incrementally between neighboring matched signal paths. The technique, called incremental signaling, is similar to dicode (1) partial response signaling except that the sequence is transmitted in parallel over a bus of wires rather than sequentially in time. Theoretical and simulated bit error rates are presented for several possible implementations of an encoder/transmitter and receiver/decoder for a digital data bus including peak detection and maximum likelihood sequence detection (MLSD). Peak detection uses C1 signal paths and results in a 3-dB performance degradation with respect to independent noise compared with fully differential signaling. The Viterbi algorithm for MLSD uses C2 signal paths but provides only a 1.25 dB improvement over peak detection due to correlated noise on the (1)-coded sequence. Modified Viterbi algorithms that use C2 signal paths are introduced to cancel the correlated noise sources, resulting in a bit error rate performance comparable with fully differential signaling. Index Terms—Chip-to-chip interface, differential signaling, maximum likelihood sequence detection. I.

Analog Viterbi decoders have recently been shown to be viable alternatives to their digital counterparts. In fact, a commercial analog class-IV partial-response sequence detector for magnetic read channels has already been reported. Analog decoders offer the advantages of reduced power and size primarily due to the elimination of the A/D. The analog Viterbi decoder described here is less complex and more robust compared to other reported realizations. The decoder is based on a new derivation of the difference-metric algorithm which is developed from an analog implementation perspective. This has resulted in a decrease in hardware complexity thereby making an analog approach more attractive for today's demanding high-speed, low-power, and small-size applications, such as magnetic diskdrive storage systems. The decoder was fabricated in a 0.8-m BiCMOS process. It consists of two time-interleaved dicodes and the interleaving circuitry. The decoder was tested at up to 100 MS/s. However, si...