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52
Power Minimization in IC Design: Principles and Applications
 ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
, 1996
"... Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for designing low powe ..."
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Cited by 197 (28 self)
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Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.
Towards a HighLevel Power Estimation Capability
 IEEE trans. on CAD
, 1996
"... We will present a power estimation technique for digital integrated circuits that operates at the register transfer level (RTL). Such a highlevel power estimation capability is required in order to provide early warning of any power problems, before the circuitlevel design has been specified. With ..."
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Cited by 96 (10 self)
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We will present a power estimation technique for digital integrated circuits that operates at the register transfer level (RTL). Such a highlevel power estimation capability is required in order to provide early warning of any power problems, before the circuitlevel design has been specified. With such early warning, the designer can explore design tradeoffs at a higher level of abstraction than previously possible, reducing design time and cost. Our estimator is based on the use of entropy as a measure of the average activity to be expected in the final implementation of a circuit, given only its Boolean functional description. This technique has been implemented and tested on a variety of circuits. The empirical results to be presented are very promising and demonstrate the feasibility and utility of this approach. y This work was supported in part by Intel Corp., Santa Clara, CA. Submitted to the IEEE Transactions on CAD, 1995. 1. Introduction The high device count and operati...
Soft Digital Signal Processing
 IEEE Transactions on Very Large Scale Integration (VLSI
, 2001
"... In this paper, we propose a framework for lowenergy digital signal processing (DSP) where the supply voltage is scaled beyond the critical voltage imposed by the requirement to match the critical path delay to the throughput. This deliberate introduction of inputdependent errors leads to degradati ..."
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Cited by 49 (4 self)
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In this paper, we propose a framework for lowenergy digital signal processing (DSP) where the supply voltage is scaled beyond the critical voltage imposed by the requirement to match the critical path delay to the throughput. This deliberate introduction of inputdependent errors leads to degradation in the algorithmic performance, which is compensated for via algorithmic noisetolerance (ANT) schemes. The resulting setup that comprises of the DSP architecture operating at subcritical voltage and the error control scheme is referred to as soft DSP. The effectiveness of the proposed scheme is enhanced when arithmetic units with a higher "delayimbalance" are employed. A prediction based errorcontrol scheme is proposed to enhance the performance of the filtering algorithm in presence of errors due to soft computations. For a frequency selective filter, it is shown that the proposed scheme pro vides 60%  81% reduction in energy dissipation for filter bandwidths up to 0.5 (where 2 corresponds to the sampling frequency f) over that achieved via conven tional architecture and voltage scaling, with a maximum of 0.5dB degradation in the output signaltonoise ratio ($NRo). It is also shown that the proposed algorithmic noisetolerance schemes can also be used to improve the performance of DSP algorithms in presence of biterror rates of upto 103 due to deep submicron (DSM) noise. I.
EnergyEfficient Signal Processing via Algorithmic NoiseTolerance
, 1999
"... In this paper, we propose a framework for lowenergy digital signal processing (DSP) where the supply voltage is scaled beyond the critical voltage required to match the critical path delay to the throughput. This deliberate introduction of inputdependent errors leads to degradation in the algorith ..."
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Cited by 42 (3 self)
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In this paper, we propose a framework for lowenergy digital signal processing (DSP) where the supply voltage is scaled beyond the critical voltage required to match the critical path delay to the throughput. This deliberate introduction of inputdependent errors leads to degradation in the algorithmic performance, which is compensated for via algorithmic noisetolerance (ANT) schemes. The resulting setup that comprises of the DSP architecture operating at subcritical voltage and the error control scheme is referred to as soft DSP. It is shown that technology scaling renders the proposed scheme more effective as the delay penalty suffered due to voltage scaling reduces due to short channel effects. The effectiveness of the proposed scheme is also enhanced when arithmetic units with a higher "delayimbalance" are employed. A prediction based errorcontrol scheme is proposed to enhance the performance of the filtering algorithm in presence of errors due to soft computations. For a frequ...
Gatelevel Power Estimation Using Tagged Probabilistic Simulation
"... In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the notion of tagged (probability) waveforms, which model the set of all possible events at the output of each circuit node. Tagg ..."
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Cited by 42 (1 self)
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In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the notion of tagged (probability) waveforms, which model the set of all possible events at the output of each circuit node. Tagged waveforms are obtained by partitioning the logic waveform space of a circuit node according to the initial and final values of each logic waveform and compacting all logic waveforms in each partition by a single tagged waveform. From the tagged waveform, one can calculate the switching activity and hence the average power consumption of the circuit node. To improve the efficiency of tagged probabilistic simulation, only tagged waveforms at the circuit inputs are exactly computed. The tagged waveforms of the remaining nodes are computed using a compositional scheme that propagates the tagged waveforms from circuit inputs to circuit outputs. We obtain significant speed up over explicit simulation methods with an average error of only 6%. This also represents a factor of 23 improvement in accuracy of power estimates over previous probabilistic simulation approaches.
HighLevel Area and Power Estimation for VLSI Circuits
, 1997
"... This paper addresses the problem of computing the area complexity of a multioutput combinational logic circuit, given only its functional description, i.e., Boolean equations, where area complexity is measured in terms of the number of gates required for an optimal multilevel implementation of the ..."
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Cited by 36 (4 self)
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This paper addresses the problem of computing the area complexity of a multioutput combinational logic circuit, given only its functional description, i.e., Boolean equations, where area complexity is measured in terms of the number of gates required for an optimal multilevel implementation of the combinational logic. The proposed area model is based on transforming the given multioutput Boolean function description into an equivalent singleoutput function. The model is empirical, and results demonstrating its feasibility and utility are presented. Also, a methodology for converting the gate count estimates, obtained from the area model, into capacitance estimates is presented. Highlevel power estimates based on the total capacitance estimates and average activity estimates are also presented.
Power Estimation in Sequential Circuits
, 1995
"... A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected, by simulation, that allow efficient power estimation for the whole ..."
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Cited by 32 (6 self)
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A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected, by simulation, that allow efficient power estimation for the whole design. An important advantage of this approach is that the desired accuracy can be specified upfront by the user; the algorithm iterates until the specified accuracy is achieved. This has been implemented and tested on a number of sequential circuits and found to be much faster than existing techniques. We can complete the analysis of a circuit with 1,452 flipflops and 19,253 gates in about 4.6 hours (the largest test case reported previously has 223 flipflops). I. INTRODUCTION The dramatic decrease in feature size and the corresponding increase in the number of devices on a chip, combined with the growing demand for portable communication and computing systems, have made power consump...
Maximum Power Estimation for CMOS Circuits Using Deterministic and Statistical Approaches
, 1995
"... Excessive instantaneous power consumption may reduce the reliability and performance of VLSI chips. Hence, to synthesize circuits with high reliability, it is imperative to efficiently obtain a precise estimation of the maximum power dissipation. However, due to the inherent inputpattern dependence ..."
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Cited by 24 (2 self)
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Excessive instantaneous power consumption may reduce the reliability and performance of VLSI chips. Hence, to synthesize circuits with high reliability, it is imperative to efficiently obtain a precise estimation of the maximum power dissipation. However, due to the inherent inputpattern dependence of the problem, it is impractical to conduct an exhaustive search for circuits with a large number of primary inputs. Hence, the practical approach is to generate a tight lower bound and an upper bound for maximum power dissipation within a reasonable amount of CPU time. In this paper, instead of using the traditional simulationbased techniques, we propose a novel approach to obtain a lower bound of the maximum power consumption using Automatic Test Generation (ATG) technique. Experiments with MCNC and ISCAS85 benchmark circuits show that our approach generates the lower bound with the quality which cannot be achieved using simulationbased techniques. In addition, a Monte Carlo based t...
Total System Energy Minimization for Wireless Image Transmission
 Journal of VLSI Signal Processing Systems
, 2001
"... In this paper, we focus on the totalsystemenergy mininfization of a wireless image transntission system including both digital and analog components. Traditionally, digital power consumption has been ignored in system design, since transnfit power has been the most significant component. Howeve ..."
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Cited by 23 (1 self)
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In this paper, we focus on the totalsystemenergy mininfization of a wireless image transntission system including both digital and analog components. Traditionally, digital power consumption has been ignored in system design, since transnfit power has been the most significant component. However, as we move to an era of picocell environments and as more complex signal processing algorithms are being used at higher data rates, the digital power consumption of these systems becomes an issue. We present an energyoptinfized image transnfission system for indoor wireless applications which exploits the variabilities in the image data and the wireless multipath channel by employing dynamic algorithm transformations and joint sourcechannel coding. The variability in the image data is characterized by the ratedistortion curve, and the variability in the channel characteristics is characterized by the pathloss and impulse response of the channel. The system hardware configuration space is characterized by the errorcorrection capability of the channel encoder/decoder, number of poweredup fingers in the RAKE receiver, and transmit power of the power amplifier. An optimization algorithm is utilized to obtain energyoptimal configurations subject to endtoend performance constraints. The proposed design is tested over QCIF images, IMT2000 channels and 0.18/m, 2.5V CMOS technology parameters. Simulation results over various images, various distances, two different channels, and two different rates show that the average energy savings in utilizing a totalsystemenergy mininfization over a fixed system (designed for the worst image, the worst channel and the maximum distance) are 53.6% and 67.3%, respectively, for shortrange (under 20m) and longrange (o...
Energy Efficient JPEG 2000 Image Transmission over PointtoPoint Wireless Networks
 In Proceedings of Global Telecommunications Conference (GLOBECOM
, 2003
"... In this paper, we propose an energy efficient JPEG 2000 image transmission system over pointto point wireless networks. The objective is to minimize the overall processing and transmission energy consumption with the expected endtoend QoS guarantee, which is achieved by jointly adjusting the s ..."
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Cited by 22 (0 self)
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In this paper, we propose an energy efficient JPEG 2000 image transmission system over pointto point wireless networks. The objective is to minimize the overall processing and transmission energy consumption with the expected endtoend QoS guarantee, which is achieved by jointly adjusting the source coding schemes, channel coding rates, and transmitter power levels in an optimal way. The advantages of the proposed system lie in three aspects: adaptivity, optimality, and low complexity. Based on the characteristics of the image content, the estimated channel conditions, and the distortion constraint, the proposed lowcomplexity joint source channel coding and power control algorithm adjusts the coding and transmission strategies adaptively, which can approximate the optimal solution with a tight bound.