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Montgomery Modular Exponentiation on Reconfigurable Hardware
, 1999
"... It is widely recognized that security issues will play a crucial role in the majority of future computer and communication systems. Central tools for achieving system security are cryptographic algorithms. For performance as well as for physical security reasons, it is often advantageous to realize ..."
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Cited by 32 (3 self)
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It is widely recognized that security issues will play a crucial role in the majority of future computer and communication systems. Central tools for achieving system security are cryptographic algorithms. For performance as well as for physical security reasons, it is often advantageous to realize cryptographic algorithms in hardware. In order to overcome the wellknown drawback of reduced flexibility that is associated with traditional ASIC solutions, this contribution proposes arithmetic architectures which are optimized for modern field programmable gate arrays (FPGAs). The proposed architectures perform modular exponentiation with very long integers. This operation is at the heart of many practical publickey algorithms such as RSA and discrete logarithm schemes. We combine the Montgomery modular multiplication algorithm with a new systolic array design, which is capable of processing a variable number of bits per array cell. The designs are flexible, allowing any choice of operan...
Systolic, LinearArray Multiplier for a Class of RightShift Algorithms
, 1994
"... A very simple multiplier cell is developed for use in a linear, purely systolic array forming a digitserial multiplier for unsigned or 2'complement operands. Each cell produces two digitproduct terms and accumulates these into a previous sum of the same weight, developing the product least signifi ..."
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Cited by 28 (0 self)
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A very simple multiplier cell is developed for use in a linear, purely systolic array forming a digitserial multiplier for unsigned or 2'complement operands. Each cell produces two digitproduct terms and accumulates these into a previous sum of the same weight, developing the product least significant digit first. Grouping two terms per cell, the ratio of active elements to latches is low, and only cells are needed for a tidl n by n multiply. A modulomultiplier is then developed by incorporating a Montgomery type of moduloreduction. Two such multipliers interconnect to form a purely systolic modulo exponentiator, capable of performing RSA encryption at very high clock frequencies, but with a low gate count and small area. It is also shown how the multiplier, with some simple backend connections, can compute modular inverses and perform modular division for a ppwer of two as modulus.
Comparison of Three Modular Reduction Functions
 IN ADVANCES IN CRYPTOLOGYCRYPTO'93, LNCS 773
, 1994
"... Three modular reduction algorithms for large integers are compared with respect to their performance in portable software: the classical algorithm, Barrett's algorithm and Montgomery's algorithm. These algorithms are a time critical step in the implementation of the modular exponentiation operation. ..."
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Cited by 26 (1 self)
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Three modular reduction algorithms for large integers are compared with respect to their performance in portable software: the classical algorithm, Barrett's algorithm and Montgomery's algorithm. These algorithms are a time critical step in the implementation of the modular exponentiation operation. For each of these algorithms their plication in the modular exponentiation operation is considered. Modular exponentiation constitutes the basis of many well known and widely used public key cryptosystems. A fast and portable modular exponentiation will considerably enhance the speed and applicability of these systems.
An RNS Montgomery Modular Multiplication Algorithm
, 1998
"... We present a new RNS modular multiplication for very large operands. The algorithm is based on Montgomery's method adapted to mixed radix, and is performed using a Residue Number System. By choosing the moduli of the RNS system reasonably large, and implementing the system on a ring of fairly simple ..."
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Cited by 25 (3 self)
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We present a new RNS modular multiplication for very large operands. The algorithm is based on Montgomery's method adapted to mixed radix, and is performed using a Residue Number System. By choosing the moduli of the RNS system reasonably large, and implementing the system on a ring of fairly simple processors, the carryfree nature of RNS arithmetic achieves an effect corresponding to a redundant highradix implementation. The algorithm can be implemented to run in O(n) time on O(n) processors, where n is the number of moduli in the RNS system. 1 Introduction Many cryptosystems employs modular multiplication with very large numbers [RSA78, FS86]. Different algorithms have been proposed in the literature [Bri90, Kor93, Wal93, Tak93, SV93, Oru95]. Most of them use redundant radix number systems and Montgomery 's modular multiplication [Mon85]. On the other hand the Residue Number System (RNS) is also of particular interest because of the parallel and carry free nature of its arithmeti...
A HighPerformance Flexible Architecture for Cryptography
 1717 in Lecture Notes in Computer Science
, 1999
"... . Cryptographic algorithms are more efficiently implemented in custom hardware than in software running on generalpurpose processors. However, systems which use hardware implementations have significant drawbacks: they are unable to respond to flaws discovered in the implemented algorithm or to cha ..."
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Cited by 25 (1 self)
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. Cryptographic algorithms are more efficiently implemented in custom hardware than in software running on generalpurpose processors. However, systems which use hardware implementations have significant drawbacks: they are unable to respond to flaws discovered in the implemented algorithm or to changes in standards. In this paper we show how reconfigurable computing offers high performance yet flexible solutions for cryptographic algorithms. We focus on PipeRench, a reconfigurable fabric that supports implementations which can yield better than customhardware performance and yet maintains all the flexibility of software based systems. PipeRench is a pipelined reconfigurable fabric which virtualizes hardware, enabling large circuits to be run on limited physical hardware. We present implementations for Crypton, IDEA, RC6, and Twofish on PipeRench and an extension of PipeRench, PipeRench . We also describe how various proposed AES algorithms could be implemented on PipeRe...
On circuits and numbers
 IEEE Transactions on Computers
, 1994
"... This work may not be copied or reproduced in whole or in part for any commercial purpose. Permission to copy in whole or in part without payment of fee is granted for nonprofit educational and research purposes provided that all such whole or partial copies include the following: a notice that such ..."
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Cited by 23 (1 self)
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This work may not be copied or reproduced in whole or in part for any commercial purpose. Permission to copy in whole or in part without payment of fee is granted for nonprofit educational and research purposes provided that all such whole or partial copies include the following: a notice that such copying is by permission of the Paris Research Laboratory of Digital Equipment Centre Technique Europe, in RueilMalmaison, France; an acknowledgement of the authors and individual contributors to the work; and all applicable portions of the copyright notice. Copying, reproducing, or republishing for any other purpose shall require a license with payment of fee to the Paris Research Laboratory. All rights reserved. ii We establish the following correspondences between the ring of 2adic integers 2Z from arithmetics and digital circuits (finite and infinite, combinational and synchronous) from electronics (Theorems 1 and 2): 1. A function is computed by a combinational circuit if and only if it is continuous over the 2adic integers 2Z: 8n 2 N � x 2 2Z � 9m 2 N: f�x��f�xmod2 m � �mod 2 n ��
A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware
"... This work proposes a new elliptic curve processor architecture for the computation of point multiplication for curves defined over fields GF (p). This is a scalable architecture in terms of area and speed specially suited for memoryrich hardware platforms such a field programmable gate arrays ( ..."
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Cited by 20 (2 self)
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This work proposes a new elliptic curve processor architecture for the computation of point multiplication for curves defined over fields GF (p). This is a scalable architecture in terms of area and speed specially suited for memoryrich hardware platforms such a field programmable gate arrays (FPGAs). This processor uses a new type of highradix Montgomery multiplier that relies on the precomputation of frequently used values and on the use of multiple processing engines.
Modular Exponentiation on Reconfigurable Hardware
, 1999
"... It is widely recognized that security issues will play a crucial role in the majority of future computer and communication systems. A central tool for achieving system security are cryptographic algorithms. For performance as well as for physical security reasons, it is often advantageous to realize ..."
Abstract

Cited by 19 (1 self)
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It is widely recognized that security issues will play a crucial role in the majority of future computer and communication systems. A central tool for achieving system security are cryptographic algorithms. For performance as well as for physical security reasons, it is often advantageous to realize cryptographic algorithms in hardware. In order to overcome the wellknown drawback of reduced flexibility that is associated with traditional ASIC solutions, this contribution proposes arithmetic architectures which are optimized for modern field programmable gate arrays (FPGAs). The proposed architectures perform modular exponentiation with very long integers. This operation is at the heart of many practical publickey algorithms such as RSA and discrete logarithm schemes. We combine two versions of Montgomery modular multiplication algorithm with new systolic array designs which are well suited for FPGA realizations. The first one is based on a radix of two and is capable of processing a ...
Untraceability in Mobile Networks
 In Proceedings of the First Annual International Conference on Mobile Computing and Networking (MobiCom
, 1995
"... User mobility is a feature that raises many new securityrelated issues and concerns. One of them is the disclosure of a mobile user's real identity during the authentication process, or other procedures specific to mobile networks. Such disclosure allows an unauthorized thirdparty to track the mob ..."
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Cited by 19 (0 self)
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User mobility is a feature that raises many new securityrelated issues and concerns. One of them is the disclosure of a mobile user's real identity during the authentication process, or other procedures specific to mobile networks. Such disclosure allows an unauthorized thirdparty to track the mobile user's movements and current whereabouts. Depending on the context, access to any information related to a mobile user's location without his consent can be a serious violation of his privacy. This new issue might be seen as a conflicting requirement with respect to authentication: untraceability requires hiding the user's identity while authentication requires the user's identity to be revealed in order to be proved. What is needed is a single mechanism reconciling both authentication and privacy of a mobile user's identification. The basic solution to this problem is the use of aliases. Aliases insure untraceability by hiding the user's real identity as well as his relationship with d...
Design and Implementation of a Coprocessor for Cryptography Applications
, 1997
"... In this paper, an ASIC suitable for cryptography applications based on modular arithmetic techniques, is presented. These applications, such as for example digital signature (DSA) and public key encryption and decryption (RSA), use, as basic operation, the modular exponentiation. This ASIC works as ..."
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Cited by 17 (0 self)
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In this paper, an ASIC suitable for cryptography applications based on modular arithmetic techniques, is presented. These applications, such as for example digital signature (DSA) and public key encryption and decryption (RSA), use, as basic operation, the modular exponentiation. This ASIC works as a coprocessor with a special set of instructions specialized on dealing with high accuracy integers, as well as on the rapid evaluation of modular multiplications and exponentiations. The algorithm, the hardware architecture, the design methodology and the results are described in detail. 1. Introduction Security has become a key issue in the world of electronic communication. Besides how fast data are transmitted, the security of these data through the communication channel arises as one of the most important problems. Though, the time overhead due to data encryption and decryption should not impose a bottleneck in the communication process. Public key cryptography (RSA), as well as othe...