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Montgomery Modular Exponentiation on Reconfigurable Hardware
, 1999
"... It is widely recognized that security issues will play a crucial role in the majority of future computer and communication systems. Central tools for achieving system security are cryptographic algorithms. For performance as well as for physical security reasons, it is often advantageous to realize ..."
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Cited by 43 (3 self)
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It is widely recognized that security issues will play a crucial role in the majority of future computer and communication systems. Central tools for achieving system security are cryptographic algorithms. For performance as well as for physical security reasons, it is often advantageous to realize cryptographic algorithms in hardware. In order to overcome the wellknown drawback of reduced flexibility that is associated with traditional ASIC solutions, this contribution proposes arithmetic architectures which are optimized for modern field programmable gate arrays (FPGAs). The proposed architectures perform modular exponentiation with very long integers. This operation is at the heart of many practical publickey algorithms such as RSA and discrete logarithm schemes. We combine the Montgomery modular multiplication algorithm with a new systolic array design, which is capable of processing a variable number of bits per array cell. The designs are flexible, allowing any choice of operan...
An RNS Montgomery modular multiplication algorithm
 IEEE Transactions on Computers
, 1998
"... ..."
Comparison of Three Modular Reduction Functions
 IN ADVANCES IN CRYPTOLOGYCRYPTO'93, LNCS 773
, 1994
"... Three modular reduction algorithms for large integers are compared with respect to their performance in portable software: the classical algorithm, Barrett's algorithm and Montgomery's algorithm. These algorithms are a time critical step in the implementation of the modular exponentiation ..."
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Cited by 31 (1 self)
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Three modular reduction algorithms for large integers are compared with respect to their performance in portable software: the classical algorithm, Barrett's algorithm and Montgomery's algorithm. These algorithms are a time critical step in the implementation of the modular exponentiation operation. For each of these algorithms their plication in the modular exponentiation operation is considered. Modular exponentiation constitutes the basis of many well known and widely used public key cryptosystems. A fast and portable modular exponentiation will considerably enhance the speed and applicability of these systems.
A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware
"... This work proposes a new elliptic curve processor architecture for the computation of point multiplication for curves defined over fields GF (p). This is a scalable architecture in terms of area and speed specially suited for memoryrich hardware platforms such a field programmable gate arrays ( ..."
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Cited by 31 (2 self)
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This work proposes a new elliptic curve processor architecture for the computation of point multiplication for curves defined over fields GF (p). This is a scalable architecture in terms of area and speed specially suited for memoryrich hardware platforms such a field programmable gate arrays (FPGAs). This processor uses a new type of highradix Montgomery multiplier that relies on the precomputation of frequently used values and on the use of multiple processing engines.
Systolic, LinearArray Multiplier for a Class of RightShift Algorithms
, 1994
"... A very simple multiplier cell is developed for use in a linear, purely systolic array forming a digitserial multiplier for unsigned or 2'complement operands. Each cell produces two digitproduct terms and accumulates these into a previous sum of the same weight, developing the product least si ..."
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Cited by 31 (0 self)
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A very simple multiplier cell is developed for use in a linear, purely systolic array forming a digitserial multiplier for unsigned or 2'complement operands. Each cell produces two digitproduct terms and accumulates these into a previous sum of the same weight, developing the product least significant digit first. Grouping two terms per cell, the ratio of active elements to latches is low, and only cells are needed for a tidl n by n multiply. A modulomultiplier is then developed by incorporating a Montgomery type of moduloreduction. Two such multipliers interconnect to form a purely systolic modulo exponentiator, capable of performing RSA encryption at very high clock frequencies, but with a low gate count and small area. It is also shown how the multiplier, with some simple backend connections, can compute modular inverses and perform modular division for a ppwer of two as modulus.
A HighPerformance Flexible Architecture for Cryptography
 1717 in Lecture Notes in Computer Science
, 1999
"... . Cryptographic algorithms are more efficiently implemented in custom hardware than in software running on generalpurpose processors. However, systems which use hardware implementations have significant drawbacks: they are unable to respond to flaws discovered in the implemented algorithm or to cha ..."
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Cited by 29 (1 self)
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. Cryptographic algorithms are more efficiently implemented in custom hardware than in software running on generalpurpose processors. However, systems which use hardware implementations have significant drawbacks: they are unable to respond to flaws discovered in the implemented algorithm or to changes in standards. In this paper we show how reconfigurable computing offers high performance yet flexible solutions for cryptographic algorithms. We focus on PipeRench, a reconfigurable fabric that supports implementations which can yield better than customhardware performance and yet maintains all the flexibility of software based systems. PipeRench is a pipelined reconfigurable fabric which virtualizes hardware, enabling large circuits to be run on limited physical hardware. We present implementations for Crypton, IDEA, RC6, and Twofish on PipeRench and an extension of PipeRench, PipeRench . We also describe how various proposed AES algorithms could be implemented on PipeRe...
Untraceability in Mobile Networks
 In Proceedings of the First Annual International Conference on Mobile Computing and Networking (MobiCom
, 1995
"... User mobility is a feature that raises many new securityrelated issues and concerns. One of them is the disclosure of a mobile user's real identity during the authentication process, or other procedures specific to mobile networks. Such disclosure allows an unauthorized thirdparty to track th ..."
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Cited by 26 (0 self)
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User mobility is a feature that raises many new securityrelated issues and concerns. One of them is the disclosure of a mobile user's real identity during the authentication process, or other procedures specific to mobile networks. Such disclosure allows an unauthorized thirdparty to track the mobile user's movements and current whereabouts. Depending on the context, access to any information related to a mobile user's location without his consent can be a serious violation of his privacy. This new issue might be seen as a conflicting requirement with respect to authentication: untraceability requires hiding the user's identity while authentication requires the user's identity to be revealed in order to be proved. What is needed is a single mechanism reconciling both authentication and privacy of a mobile user's identification. The basic solution to this problem is the use of aliases. Aliases insure untraceability by hiding the user's real identity as well as his relationship with d...
ASC: a stream compiler for computing with FPGAs
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2006
"... Abstract—A stream compiler (ASC) for computing with field programmable gate arrays (FPGAs) emerges from the ambition to bridge the hardwaredesign productivity gap where the number of available transistors grows more rapidly than the productivity of very large scale integration (VLSI) and FPGA compu ..."
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Cited by 25 (7 self)
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Abstract—A stream compiler (ASC) for computing with field programmable gate arrays (FPGAs) emerges from the ambition to bridge the hardwaredesign productivity gap where the number of available transistors grows more rapidly than the productivity of very large scale integration (VLSI) and FPGA computeraideddesign (CAD) tools. ASC addresses this problem with a softwarelike programming interface to hardware design (FPGAs) while keeping the performance of handdesigned circuits at the same time. ASC improves productivity by letting the programmer optimize the implementation on the algorithm level, the architecture level, the arithmetic level, and the gate level, all within the same C++ program. The increased productivity of ASC is applied to the hardware acceleration of a wide range of applications. Traditionally, hardware accelerators are tediously handcrafted to achieve top performance. ASC simplifies designspace exploration of hardware accelerators by transforming the hardwaredesign task into a softwaredesign process, using only “GNU compiler collection (GCC)” and “make ” to obtain a hardware netlist. From experience, the hardwaredesign productivity and ease of use are close to pure software development. This paper presents results and case studies with optimizations that are: 1) on the gate level—Kasumi and International Data Encryption Algorithm (IDEA) encryptions; 2) on the arithmetic level—redundant addition and multiplication function evaluation for twodimensional (2D) rotation; and 3) on the architecture level—Wavelet and Lempel–Ziv (LZ)like compression. Index Terms—Design space exploration, FPGAs, hardware design. I.
Design and Implementation of a Coprocessor for Cryptography Applications
, 1997
"... In this paper, an ASIC suitable for cryptography applications based on modular arithmetic techniques, is presented. These applications, such as for example digital signature (DSA) and public key encryption and decryption (RSA), use, as basic operation, the modular exponentiation. This ASIC works as ..."
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Cited by 23 (0 self)
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In this paper, an ASIC suitable for cryptography applications based on modular arithmetic techniques, is presented. These applications, such as for example digital signature (DSA) and public key encryption and decryption (RSA), use, as basic operation, the modular exponentiation. This ASIC works as a coprocessor with a special set of instructions specialized on dealing with high accuracy integers, as well as on the rapid evaluation of modular multiplications and exponentiations. The algorithm, the hardware architecture, the design methodology and the results are described in detail. 1. Introduction Security has become a key issue in the world of electronic communication. Besides how fast data are transmitted, the security of these data through the communication channel arises as one of the most important problems. Though, the time overhead due to data encryption and decryption should not impose a bottleneck in the communication process. Public key cryptography (RSA), as well as othe...