Abstract—This paper describes a 10-b 20-Msample/s analogto-digital converter fabricated in a 0.9-pm CMOS technology. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-anddistortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies 8.7 mmz and dissipates 240 mW. I.

A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free-dynamic range (SFDR) of 93.3 dB, a total-harmonic distortion (THD) of –92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least-significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm 2 in 0.35-µm CMOS.

Reduction of the power dissipation associated with high speed sampling and quantization is a major problem in many applications, including portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers,