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Implementing the Elliptic Curve Method of Factoring in Reconfigurable Hardware
"... A novel portable hardware architecture of the Elliptic Curve Method of factoring, designed and optimized for application in the relation collection step of the Number Field Sieve, is described and analyzed. A comparison with an earlier proofofconcept design by Pelzl, Simka, et al. has been perform ..."
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A novel portable hardware architecture of the Elliptic Curve Method of factoring, designed and optimized for application in the relation collection step of the Number Field Sieve, is described and analyzed. A comparison with an earlier proofofconcept design by Pelzl, Simka, et al. has been performed, and a substantial improvement has been demonstrated in terms of both the execution time and the areatime product. The ECM architecture has been ported across five different families of FPGA devices in order to select the family with the best performance to cost ratio. A timing comparison with the highly optimized software implementation, GMPECM, has been performed. Our results indicate that lowcost families of FPGAs, such as Spartan3 and Spartan3E, offer at least an order of magnitude improvement over the same generation of microprocessors in terms of the performance to cost ratio. 1.
FPGA and ASIC implementation of rho and p1 methods of factoring
, 2007
"... FPGA and ASIC Implementation of rho and p1 methods of factoring ..."
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FPGA and ASIC Implementation of rho and p1 methods of factoring
Areatime efficient implementation of the elliptic curve method of factoring in reconfigurable hardware for application in the number field sieve
 IEEE Transactions on Computers
, 2009
"... Abstract — A novel portable hardware architecture of the Elliptic Curve Method of factoring, designed and optimized for application in the relation collection step of the Number Field Sieve, is described and analyzed. A comparison with an earlier proofofconcept design by Pelzl, ˇSimka, et al. has ..."
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Abstract — A novel portable hardware architecture of the Elliptic Curve Method of factoring, designed and optimized for application in the relation collection step of the Number Field Sieve, is described and analyzed. A comparison with an earlier proofofconcept design by Pelzl, ˇSimka, et al. has been performed, and a substantial improvement has been demonstrated in terms of both the execution time and the areatime product. The ECM architecture has been ported across five different families of FPGA devices in order to select the family with the best performance to cost ratio. A timing comparison with the highly optimized software implementation, GMPECM, has been performed. Our results indicate that lowcost families of FPGAs, such as Spartan3 and Spartan3E, offer at least an order of magnitude improvement over the same generation of microprocessors in terms of the performance to cost ratio, without the use of embedded FPGA resources, such as embedded multipliers. Index Terms — Cipherbreaking, factoring, ECM, FPGA, NFS I.
Maciej Wielgosz∗ COMPUTATION ACCELERATION ON SGI RASC: FPGA BASED RECONFIGURABLE COMPUTING HARDWARE
"... In this paper a novel method of computation using FPGA technology is presented. In several cases this method provides a calculations speedup with respect to the General Purpose Processors (GPP). The main concept of this approach is based on such a design of computing hardware architecture to fit a ..."
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In this paper a novel method of computation using FPGA technology is presented. In several cases this method provides a calculations speedup with respect to the General Purpose Processors (GPP). The main concept of this approach is based on such a design of computing hardware architecture to fit algorithm dataflow and best utilize well known computing techniques as pipelining and parallelism. Configurable hardware is used as a implementation platform for custom designed hardware. Paper will present implementation results of algorithms those are used in such areas as cryptography, data analysis and scientific computation. The other promising areas of new technology utilization will also be mentioned, bioinformatics for instance. Mentioned algorithms were designed, tested and implemented on SGI RASC platform. RASC module is a part of Cyfronet’s SGI Altix 4700 SMP system. We will also present RASC modern architecture. In principle it consists of FPGA chips and very fast, 128bit wide local memory. Design tools avaliable for designers will also be presented.