Asynchronous design has enjoyed a revival of interest recently, as designers seek to eliminate penalties of traditional synchronous design. In principle, asynchronous methods promise to avoid overhead due to clock skew, worst-case design assumptions and resynchronization of asynchronous external inputs. In practice, however, many asynchronous design methods suffer from a number of problems: unsound algorithms (implementations may have hazards), harsh restrictions on the range of designs that can be handled (single-input changes only), incompatibility with existing design styles and inefficiency in the resulting circuits. This thesis presents a new locally-clocked design method for the synthesis of asynchronous controllers. The method has been automated, is proven correct and produces high-performance implementations which are hazard-free at the gate-level. Implementations allow multiple-input changes and handle a relatively unconstrained class of behaviors (called "burst-mode" specifications). The method produces state-machine implementations with a minimal or near-minimal number of states. Implementations can be easily built in such common VLSI design styles as gate-array, standard cell and full-custom. Realizations typically have the latency of

ions for Mobile Computing Peter J. McCann, Gruia-Catalin Roman Abstract--- Recent advances in wireless networking technology and the increasing demand for ubiquitous, mobile connectivity demonstrate the importance of providing reliable systems for managing reconfiguration and disconnection of components. Design of such systems requires tools and techniques appropriate to the task. Many formal models of computation, including UNITY, are not adequate for expressing reconfiguration and disconnection and are therefore inappropriate vehicles for investigating the impact of mobility on the construction of modular and composable systems. Algebraic formalisms such as the ß-calculus have been proposed for modeling mobility. This paper addresses the question of whether UNITY, a state-based formalism with a foundation in temporal logic, can be extended to address concurrent, mobile systems. In the process, we examine some new abstractions for communication among mobile components that express re...

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A novel formal theory of concurrent systems is introduced that does not assume any atomic operations. The execution of a concurrent program is modeled as an abstract set of operation executions with two temporal ordering relations: "precedence" and "can causally a#ect". A primitive interprocess communication mechanism is then defined. In Part II, the mutual exclusion is expressed precisely in terms of this model, and solutions using the communication mechanism are given. Contents 1 Introduction 2 2 The Model 2 2.1 Physical Considerations . . . . . . . . . . . . . . . . . . . . . 3 2.2 System Executions . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 Higher-Level Views . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Interprocess Communication 9 4 Processes 14 5 Multiple-Reader Variables 17 6 Discussion of the Assumptions 18 7 Conclusion 19 1 1 Introduction The mutual exclusion problem was first described and solved by Dijkstra in [3]. In this problem, there is a collection...

This paper describes a new technique for integrating asynchronous modules within a high-speed synchronous pipeline. Our design eliminates potential metastability problems by using a clock generated by a stoppable ring oscillator, which is capable of driving the large clock load found in present day microprocessors. Using the ATACS design tool, we designed highly optimized transistor-level circuits to control the ring oscillator and generate the clock and handshake signals with minimal overhead. Our interface architecture requires no redesign of the synchronous circuitry. Incorporating asynchronous modules in a highspeed pipeline improves performance by exploiting datadependent delay variations. Since the speed of the synchronous circuitry tracks the speed of the ring oscillator under different processes, temperatures, and voltages, the entire chip operates at the speed dictated by the current operating conditions, rather than being governed by the worst-case conditions. These two fact...

This paper describes a novel communication scheme, which is guaranteed to be free of synchronization failures, amongst multiple synchronous modules operating independently. In this scheme, communication between every pair of modules is done through an asynchronous FIFO channel; communication between a module and the FIFO is done using a request/acknowledgehandshaking. Synchronization of handshaking signals to the local module clock is done in an unconventional way [17, 15, 3, 12, 5] --- the local clock built out of a ring oscillator is paused or stretched, if necessary, to ensure that the handshaking signal satisfies setup and hold time constraints with respect to the local clock. We constructed a test bed consisting of two synchronous modules with pausible clocking control and an asynchronous FIFO on a MOSIS 1:2¯m CMOS chip. The resulting system functions reliably up to the local clock frequency of 220MHz (according to SPICE simulation) --- the maximum clock rate is limited by the rin...

Pipeline synchronization is a simple, low-cost, highbandwidth, high-reliability solution to interfaces between synchronous and asynchronous systems, or between synchronous systems operating from different clocks. The technique can sustain maximum communication bandwidth while achieving an arbitrarily low, nonzero probability of synchronization failure, P f , with the price in both latency and chip area being O(log 1 Pf ). Pipeline synchronization has been successfully applied to high-performance inter-computer communication in multicomputers [13, 15] and local-area networks [3, 7]. 1 Problem Specification Given the required rate of data transfer of E events per second between an asynchronous and a synchronous system, with each event delivering W bits of information, design an interface that will guarantee that the probability of synchronization failure be less than a given P f ? 0. The assumption is that the flow control is implemented as either a two-phase or four-phase signalin...

SHILPA is system for the high-level synthesis of self-timed circuits. It takes behavioral descriptions in a process+functional language called hopCP and produces a netlist for the Actel FPGA, supported by the VIE Wlogic tools. hopCP descriptions are initially translated into an intermediate-form based on hyper-graphs called HFG. SHILPA then applies action re-finement, which is a technique for transforming HFGs into asynchronous hardware by a series of graph-based transformation rules. Action refinement is character-ized by incremental resource allocation and control decomposition. The major contributions of the pro-posed work are: (i) the source language hopCP which is equipped with shared variables, broadcast channels, and barrier synchronization, that are constructs well suited for system-level hardware specification; (ti) use of flow analysis techniques to optimize resource alloca-tion, to implement guarded commands eficiently, and ensure that shared variables are used ‘safely ” (poten-tially concurrent reads and writes are detected); (iii) a self-timed macromodule libra y for Actel FPGA imple-mentation. 1

Hybrid automata have been introduced in both control engineering and computer science as a formal model for the dynamics of hybrid discrete-continuous systems. In the case of so-called linear hybrid automata this formalization supports semi-decision procedures for state reachability, yet no decision procedures due to inherent undecidability. Thus, unlike finite or timed automata, already linear hybrid automata are out-of-scope of fully automatic verification. In this article, we devise a new semi-decision method for safety of linear and polynomial hybrid systems which may only fail on pathological, practically uninteresting cases. These remaining cases are such that their safety depends on the complete absence of noise, a situation unlikely to occur in real hybrid systems. Furthermore, we show that if low probability effects of noise are ignored akin to the way they are suppressed in digital modelling then safety becomes fully decidable. Keywords: Hybrid Systems, Automatic Verification

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