In computer graphics, rendering is the process by which an abstract description of a scene is converted to an image. When the scene is complex, or when high-quality images or high frame rates are required, the rendering process becomes computationally demanding. To provide the necessary levels of performance, parallel computing techniques must be brought to bear. Although parallelism has been exploited in computer graphics since the early days of the field, its initial use was primarily in specialized applications. The VLSI revolution of the late 1970Õs and the advent of scalable parallel computers during the late 1980Õs changed this situation. Today, parallel hardware is routinely used in graphics workstations, and numerous software-based rendering systems have been developed for general-purpose parallel architectures. This article provides a broad introduction to the subject of parallel rendering, encompassing both hardware and software systems. The focus is on the underlying concepts and the issues which arise in the design of parallel rendering algorithms and systems. We examine the different types of parallelism and how they can be applied in rendering applications. Concepts from parallel computing, such as data decomposition, task granularity, scalability, and load balancing, are considered in relation to the rendering

In this paper we describe the implementation of VISA, our Virtual Internet SCSI Adapter. VISA was built to evaluate the performance impact on the host operating system of using IP to communicate with peripherals, especially storage devices. We have built and benchmarked file systems on VISA-attached emulated disk drives using UDP/IP. By using IP, we expect to take advantage of its scaling characteristics and support for heterogeneous media to build large, long-lived systems. Detailed file system and network CPU utilization and performance data indicate that it is possible for UDP/IP to reach more than 80% of SCSI's maximum throughput without the use of network coprocessors. We conclude that IP is a viable alternative to special-purpose storage network protocols, and presents numerous advantages. 1 Introduction Storage system architectures are increasingly network-oriented, exploiting the ubiquity of networks to replace the direct host channel. Peripherals attached directly to network...

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Moore’s Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneous CMP design for non-rendering workloads that integrates IA32 CPU cores with non-IA32 GPU-class multicores, extending the current state-of-the-art CPU-GPU integration that physically “fuses ” existing CPU and GPU designs. Pangaea introduces (1) a resource repartitioning of the GPU, where the hardware budget dedicated for 3Dspecific graphics processing is used to build more generalpurpose GPU cores, and (2) a 3-instruction extension to the IA32 ISA that supports tighter architectural integration and fine-grain shared memory collaborative multithreading between the IA32 CPU cores and the non-IA32 GPU cores. We implement Pangaea and the current CPU-GPU designs in fully-functional synthesizable RTL based on the production quality RTL of an IA32 CPU and an Intel GMA X4500 GPU. On a 65 nm ASIC process technology, the legacy graphics-specific fixed-function hardware has the area of 9 GPU cores and total power consumption of 5 GPU cores. With the ISA extensions, the latency from the time an IA32 core spawns a GPU thread to the time the thread begins execution is reduced from thousands of cycles to fewer than 30 cycles. Pangaea is synthesized on a FPGA-based prototype and runs off-the-shelf IA32 OSes. A set of general-purpose non-graphics workloads demonstrate speedups of up to 8.8×.

High-bandwidth TCP/IP networking places a significant burden on end hosts. We argue that this issue should be addressed by integrating simple network interface controllers (NICs) more closely with host CPUs, not by pushing additional computation out to the NICs. We present a simple integrated NIC design (SINIC) that is significantly less complex and more flexible than a conventional DMA-descriptor-based NIC but performs as well or better than the conventional NIC when both are integrated onto the processor die. V-SINIC, an extended version of SINIC, provides virtual per-packet registers, enabling packet-level parallel processing while maintaining a FIFO model. V-SINIC also enables deferring the copy of the packet payload on receive, which we exploit to implement a zero-copy receive optimization in the Linux 2.6 kernel. This optimization improves bandwidth by over 50 % on a receive-oriented microbenchmark. 1

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ing the Graphics Database Application Application Domain Graphics System : Flow of Control : Flow of Data Controller Renderer External Signals Application Database Temporal Graphics Database Figure 3: Schematic of the Abstract Database Model The abstract database model, which I introduce here, is more complex than the retained-mode model. An additional component, the controller shown in Figure 3, attests to this complexity. Since this model successfully addresses the shortcomings of the retained-mode model, most of today's graphics systems [34] [42] [22] employ it as their graphics subsystem. As in the previous section, I describe the abstract database model by explaining its key components, i.e., the database, the controller, the renderer, and the application, and their relationship to each other. The most dramatic change, which necessitates the addition of the controller component, occurs in the structure of the graphics database. The graphics database is extended to be temporal, n...

this paper, his spirit and joy are revealed: I, for one, am and will always remain a practicing technologist. When denied my minimum daily adult dose of technology, I get grouchy. I believe that technology is fun, especially when computers are involved, a sort of grand game or puzzle with ever so neat parts to fit together. I have turned down several lucrative administrative jobs because they would deny me that fun. If the technology you do isn't fun for you, you may wish to seek other employment. Without the fun, none of us would go on. Dr. Sutherland is presently Vice President and Fellow of Sun Microsystems, Inc. ---Ed. 4

This paper summarises the author's views on current developments in interactive scientific visualisation. It is based on a talk presented at the Eurographics '89 conference, held in Hamburg in September 1989. The paper takes issue with the direction of some current work and identifies areas where new ideas are needed. It has three main sections: data presentation methods, current visualisation system architectures, and a new approach based on parallel processing. 1 Introduction The upsurge of interest in visualisation was given a major impetus by a report prepared for the National Science Foundation in the USA (the ViSC report) [16]. The main thrust of this was to examine how the USA could remain competitive in this area, and therefore what research should be funded by the government. A major problem identified was how researchers could assimilate the truly vast amounts of data being poured out by supercomputers --- what the report termed "firehoses of data". The report recommended a s...

this memory behavior for extensive low-level traces collected on a DECstation 3100 workstation. This discussion motivates the development of different caching strategies studied in Chapter 7. Finally, Chapter 8 summarizes the contributions of this research.