Data structures for Boolean functions build an essential component of design automation tools, especially in the area of logic synthesis. The state of the art data structure is the ordered binary decision diagram (OBDD), which results from general binary decision diagrams (BDDs), also called branching programs, by ordering restrictions. In the context of EXOR-based logic synthesis another type of decision diagram (DD), called (ordered) functional decision diagram ((O)FDD) becomes increasingly important. We study the relation between (ordered, free) BDDs and FDDs. Both, BDDs and FDDs, result from DDs by defining the represented function in different ways. If the underlying DD is complete, the relation between both types of interpretation can be described by a Boolean transformation . This allows us to relate the FDD-size of f and the BDD-size of (f) also in the case that the corresponding DDs are free or ordered, but not (necessarily) complete. We use this property to derive...

In this paper a polynomial time algorithm for the minimization of Fixed Polarity Reed-Muller Expressions (FPRMs) for totally symmetric functions based on Ordered Functional Decision Diagrams (OFDDs) is presented. A generalization to partially symmetric functions is investigated. The algorithm has been implemented as the program Sympathy. Experimental results in comparison to previously published methods are given to show the efficiency of the approach. 1 Introduction The high complexity of modern VLSI circuitry has shown an increasing demand for synthesis tools. In the last few years synthesis based on AND/EXOR realizations has gained more and more interest [9], because AND/EXOR realizations are very efficient for large classes of circuits, e.g., arithmetic circuits, error correcting circuits and circuits for tele-communication [15, 16]. For these classes EXOR-circuits derived from Reed-Muller Expressions need less gates for the representation of a Boolean function and drastically r...

A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed--Muller expansions have been introduced in the synthesis of multilevel circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology not only can achieve lower area than other similar tools, but that it achieves better testability compared to available testability enhancement tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations successfully contributed toward generating smaller circuits compared to other state-ofthe -art logic optimization tools.

It is often stated that AND#EXOR circuits are much easier testable than AND#OR circuits. This statement only holds for restricted classes of AND#EXOR expressions# like positive polarity Reed# Muller expressions and #xed polarity Reed#Muller ex# pressions. For these two classes of circuits good deter# ministic testability properties are known. In this paper we show that for these circuits also good random pat# tern testability can be proven. An input probability distribution is given which yields a short expected test length for biased random patterns. This is the #rst time that theoretical results on random pattern testa# bility arepresented for 2#level AND#EXOR circuit re# alizations of arbitrary Boolean functions. For more general classes of 2#level AND#EXOR circuits analogous results are not proven. We present experimental results that show that in general mini# mized 2#level AND#OR circuits are as well #or badly# testable as minimized 2#level AND#EXOR circuits. 1 Introduction M...

In this paper a new concept of Universal XOR Canonical Forms is presented. Such forms include all well-known families of AND/XOR canonical forms as special cases. A general mathematical treatment of these forms is presented. It is shown that utilizing linear group theory, many properties and classes of these canonical forms can be studied. By this approach, the number of possible XOR canonical forms is shown to be enormous. Several operators to create various AND/OR/XOR canonical forms are also introduced. Such operators, which generalize the Kronecker tensor product, limit these canonical forms to the ones finding applications in most technologies. 1 Introduction The XOR logic is finding more interest due to its inherent characteristics, availability of new synthesis tools, and the new technologies which make efficient realization of this logic possible. In terms of inherent efficiency of XOR logic, it has been shown that AND/XOR PLAs on average are more compact than AND/OR PLAs [17]...

We present two new classes of 2-level AND/XOR expressions: the class RKRO of Reduced Kronecker Expressions and the class GKRO of Generalized Kronecker Expressions. GKRO contains RKRO and KRO, the well-known class of Kronecker Expressions [Sas93b] as a subclass. There is a close relation between RKROs, KROs, GKROs and Ordered Kronecker Functional Decision Diagrams (OKFDDs) [DST + 94], that together with efficient OKFDD algorithms can be utilized for (exact and heuristical) minimization of RKROs, KROs and GKROs. In this paper we concentrate on RKROs and KROs and propose several algorithms for their minimization. Experimental results are given to show the efficiency of our approach. For the first time efficient minimized 2-level AND/XOR expressions are determined for benchmark functions with more than 100 variables. Furthermore, we compare our solutions to results obtainable for other classes of AND/XOR forms. In particular, RKROs are much smaller than FPRMs and also turn ou...