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Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
 in Proc. of 16th International Conference on VLSI Design
, 2003
"... In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number of constraints. By introducing two additional variables per gate, namely, the fastest and the slowest arrival times, besides the gate delay,we ..."
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In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number of constraints. By introducing two additional variables per gate, namely, the fastest and the slowest arrival times, besides the gate delay,we reduce the number of the LP constraints to be linear in circuit size. For example, the 469gate c880 circuit requires 3,611 constraints as compared to the 6.95 million constraints needed with the previous method. The reduced constraints provably produce the same exact LP solution as obtained by the exponential set of constraints. For the rst time, we are able to optimize all ISCAS'85 benchmarks. For the c7552 circuit, when the input to output delay is constrained not to increase, a design with 366 delay bu ers consumes only 34 % peak and 38 % average power as compared to an unoptimized design. As shown in previous work, the use of delay bu ers is essential in this case. The practicality of the design is demonstrated by implementing an optimized 4bit ALU circuit for which the power consumption was obtained by a circuitlevel simulator. 1.
Variable Input Delay CMOS Logic for Low Power Design
 Auburn University
, 2005
"... Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional CMOS gate is designed to have the same i ..."
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Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. We propose a new gate design that has different delays along various input to output paths within the gate. This is accomplished by inserting selectively sized “permanently on ” series transistors at the inputs of the logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitchfree minimum dynamic power implementation of a digital circuit. Applying a previously described linear programming method to the c7552 benchmark circuit, we obtained a power saving of 58 % over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. All circuits had the same overall delay. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on noncritical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers. 1
Efficient and Accurate Gate Sizing with Piecewise Convex Delay Models
 DAC 2005
, 2005
"... We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model is used in a new version of a gatesizing tool called Forge, which not only exhibits optimality, but also efficiently pr ..."
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We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model is used in a new version of a gatesizing tool called Forge, which not only exhibits optimality, but also efficiently produces the area versus delay tradeoff curve for a block in one step. Forge includes a realistic delay propagation scheme that combines arrival times and slewrates. Forge is 6.4X faster than a commercial transistor sizing tool, while achieving better delay targets and uses 28 % less transistor area for specific delay targets, on average.
Fast Comparisons of Circuit Implementations
, 2005
"... Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Postprocessing transforms, such as transistor sizing, can significantly improve circuit performance by optimizing critical paths to meet timing specifications. However, most transistor ..."
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Cited by 5 (1 self)
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Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Postprocessing transforms, such as transistor sizing, can significantly improve circuit performance by optimizing critical paths to meet timing specifications. However, most transistor sizing tools have high execution times, and the possible delay gains due to sizing, and the associated costs are not known prior to sizing. In this paper, we present two metrics for comparing different implementations—the minimum achievable delay and the cost of achieving a target delay—and show how these can be estimated without running a sizing tool. Using these fast and accurate performance estimators, a designer can determine the tradeoffs between multiple functionally identical implementations, and size only the selected implementation.
Gate Sizing for Large CellBased Designs
, 2009
"... Abstract—Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices and realistic timing models. The approach iteratively assigns signal slew targets to all source pins of the chip a ..."
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Abstract—Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices and realistic timing models. The approach iteratively assigns signal slew targets to all source pins of the chip and chooses discrete layouts of minimum size preserving the slew targets. Using slew targets instead of delay budgets, accurate estimates for the input slews are available during the sizing step. Slew targets are updated by an estimate of the local slew gradient. To demonstrate the effectiveness, we propose a new heuristic to estimate lower bounds for the worst path delay. On average, we violate these bounds by 6%. A subsequent local search decreases this gap quickly to 2%. This twostage approach is capable of sizing designs with more than 5.8 million cells within 2.5 hours and thus helping to decrease turnaround times of multimillion cell designs. I.
Timing Budgeting under Arbitrary Process Variations ∗
"... Timing budgeting under process variations is an important step in a statistical optimization flow. We propose a novel formulation of the problem where budgets are statistical instead of deterministic as in existing works. This new formulation considers the changes of both the means and variances of ..."
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Timing budgeting under process variations is an important step in a statistical optimization flow. We propose a novel formulation of the problem where budgets are statistical instead of deterministic as in existing works. This new formulation considers the changes of both the means and variances of delays, and thus can reduce the timing violation introduced by ignoring the changes of variances. We transform the problem to a linear programming problem using a robust optimization technique. Our approach can be used in latestage design where the detailed distribution information is known, and is most useful in earlystage design since our approach does not assume specific underlying distributions. In addition, with the help of blocklevel timing budgeting, our approach can reduce the timing pessimism. Our approach is applied to the leakage power minimization problem. The results demonstrate that our approach can reduce timing violation from 690ps to 0ps, and the worst total leakage power by 17.50 % on average. 1
Mixed Algebraic and Boolean Symbolic Analysis of Switched Linear Networks: Theory and Applications to Coupled Gate and Interconnect Delay Modeling
, 2003
"... Abstraction of digital MOS circuits as switchlevel networks has proven very useful for VLSI automation. Symbolic analysis of switchlevel networks by representing the signal at the gate of a MOS transistor as a Boolean variable has been shown to be efficient for verification in terms of functional ..."
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Abstraction of digital MOS circuits as switchlevel networks has proven very useful for VLSI automation. Symbolic analysis of switchlevel networks by representing the signal at the gate of a MOS transistor as a Boolean variable has been shown to be efficient for verification in terms of functionality and timing. For this work, in addition to expressing the signal at the gate of MOS transistors as Boolean variables, we represent the design parameters of the transistors as algebraic symbols. In this paper, we present the theory for unified symbolic analysis in terms of both algebraic and Boolean symbols. Our formulation is general and is valid for extensions of conventional switched linear networks with various circuit elements like passive elements, current sources, etc. The theory developed for mixed algebraic and Boolean symbolic analysis is applied for symbolic delay estimation in logicstages with interconnects. Instead of conventional numeric delay estimation techniques, our method provides a single closedform analytic delay expression that is symbolic in terms of both Boolean variables and the geometric design parameters of transistors and interconnects. Such expressions provide accurate estimations of signal delay over any input pattern and extensive variation in design variables like width and lengths of transistors