Abstract-In this paper, we consider the problem of selecting an implementation of each circuit module from a cell library so as to satisfy overall delay and area (or delay and power) requirements. Two versions of the circuit implementation problem, basic circuit implementation problem and the general circuit implementation problem are shown to be NP-hard. A pseudo-polynomial time algorithm for the basic circuit imple-mentation problem on series-parallel circuits is developed, and heuristics for the basic circuit implementation problem on gen-eral circuits are formulated and experimented with. I.

In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and optimize the kmost critical paths in the circuit and their neighboring cells. More precisely in each iteration, we perform three operations: a) reposition the immediate fan-outs of the gates on the k-most critical paths; b) size down the immediate fan-outs of the gates on the k-most critical paths; c) simultaneously reposition and resize the gates on the k-most critical paths. Each of these operations is formulated and solved as a mathematical program by using efficient solution techniques. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches which separate gate sizing from gate placement. 1

We consider the problem of selectively upgrading some of the modules in a circuit so as to meet a specified performance level. The upgrading of a module involves replacing it with an equivalent module with zero delay (effectively) and this replacement has a cost or weight associated with. We show that some versions of the minimum cost upgrading problem are NP-hard while others are polynomially solvable. Several heuristics for the general problem are proposed and evaluated experimentally. Keywords And Phrases Module upgrading, performance, delay, complexity, NP-hard, heuristics + This research was supported, in part, by the National Science Foundation under grant MIP86-17374. - 2 - 1. Introduction Often, a circuit can be modeled as a directed acyclic graph (dag) G in which there is a delay, d(v), associated with each vertex, v [CHAN90, GHAN87, MCGE90]. The dag vertices represent circuit modules while interconnects are modeled by dag edges. The delay, d(v), associated with vertex v of ...

Gate resizing for minimum circuit delay is a fundamental problem in the performance optimization of gate-level circuits. In this paper, we study the complexity of two different minimum-delay gate resizing problems for combinational circuits composed of singleoutput gates. The first problem is that of gate resizing for minimum circuit delay under the load-dependent delay model. The second problem is a variant of the first, where we relax the delay model to a load-independent one, but impose load constraints instead, i.e., each gate output is not allowed to drive a capacitive load that exceeds its drive capacity. The goal, as before, is to minimize the delay through the circuit. To the best of our knowledge, there has been no published result on the complexity of these problems. In this paper, we prove that both problems are NP-complete. The proofs are inspired by Murgai's work [6], in which the global fanout optimization problem under a fixed net topology was shown to be NP-complete. These results, along with previously published ones, establish that gate resizing is a hard problem except under the most simplistic assumptions.

In most libraries, gate parameters such as the pin-to-pin intrinsic delays, load-dependent coefficients, and input pin capacitances have different values for rising and falling signals. Most performance optimization algorithms, however, assume a single value for each parameter.

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Implementation platform selection is an important component of hardware--software codesign process which selects, for a given computation, the most suitable implementation platform. In this paper, we study the complementary component of hardware--software codesign, algorithm selection. Given a set of specifications for the targeted application, algorithm selection refers to choosing the most suitable completely specified computational structure for a given set of design goals and constraints, among several functionally equivalent alternatives. While implementation platform selection has been recently widely and vigorously studied, the algorithm selection problem has not been studied in computer-aided design domain until now.

Abstract—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard [1]. Several (suboptimal) gate sizing heuristics have been proposed over the past two decades, but research has suffered from the lack of any systematic way of assessing the quality of the proposed algorithms. We develop a method to generate benchmark circuits (called eyecharts) of arbitrary size along with a method to compute their optimal solutions using dynamic programming. We evaluate the suboptimalities of some popular gate sizing algorithms. Eyecharts help diagnose the weaknesses of existing gate sizing algorithms, enable systematic and quantitative comparison of sizing algorithms, and catalyze further gate sizing research. Our results show that common sizing methods (including commercial tools) can be suboptimal by as much as 54 % (Vt-assignment), 46 % (gate sizing) and 49 % (gate-length biasing) for realistic libraries and circuit topologies.