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19
A near optimal algorithm for technology mapping minimizing area under delay constraints”, DAC92
, 1992
"... We examine the problem of mapping a Boolean network using gates from a finite size cell library. The objective is to minimize the total gate area subject to constraints on signal arrival time at the primary outputs. Our approach consists of two steps: In the first step, we compute delay functions (w ..."
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Cited by 38 (7 self)
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We examine the problem of mapping a Boolean network using gates from a finite size cell library. The objective is to minimize the total gate area subject to constraints on signal arrival time at the primary outputs. Our approach consists of two steps: In the first step, we compute delay functions (which capture arrival time – gate area tradeoffs) at all nodes in the network, and in the second step we generate the mapping solution based on the computed delay functions and the required times at the primary outputs. For a NANDdecomposed tree, subject to load calculation errors, this two step approach finds the minimum area mapping satisfying all delay constraints if such solution exists. The algorithm has polynomial run time on a nodebalanced tree and is easily extended to mapping a directed acyclic graph (DAG). Our results compare favorably with those of MIS2.2 mapper. 1
On the circuit implementation problem
 IEEE Trans. on ComputerAided Design of Integrated Circuits and Systems
, 1992
"... AbstractIn this paper, we consider the problem of selecting an implementation of each circuit module from a cell library so as to satisfy overall delay and area (or delay and power) requirements. Two versions of the circuit implementation problem, basic circuit implementation problem and the genera ..."
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Cited by 26 (0 self)
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AbstractIn this paper, we consider the problem of selecting an implementation of each circuit module from a cell library so as to satisfy overall delay and area (or delay and power) requirements. Two versions of the circuit implementation problem, basic circuit implementation problem and the general circuit implementation problem are shown to be NPhard. A pseudopolynomial time algorithm for the basic circuit implementation problem on seriesparallel circuits is developed, and heuristics for the basic circuit implementation problem on general circuits are formulated and experimented with. I.
A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment
 IEEE Trans. on CAD
"... Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivitydriven heuristics or based on rounding continuous optimization solutions. Sensitivitydriven heuristics are easily trapped in l ..."
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Cited by 13 (2 self)
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Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivitydriven heuristics or based on rounding continuous optimization solutions. Sensitivitydriven heuristics are easily trapped in local optimum and the rounding is subject to remarkable errors. In this paper, we propose a systematic combinatorial approach for simultaneous gate sizing and Vt assignment. The core ideas of this approach include consistency relaxation and coupled bidirectional search. Our algorithm is compared with a stateoftheart previous work on benchmark circuits. The results from our algorithm can lead to about 24 % less power dissipation subject to the same timing constraints.
Simultaneous Gate Sizing and Placement
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2000
"... In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and op ..."
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Cited by 13 (3 self)
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In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and optimize the kmost critical paths in the circuit and their neighboring cells. More precisely in each iteration, we perform three operations: a) reposition the immediate fanouts of the gates on the kmost critical paths; b) size down the immediate fanouts of the gates on the kmost critical paths; c) simultaneously reposition and resize the gates on the kmost critical paths. Each of these operations is formulated and solved as a mathematical program by using efficient solution techniques. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches which separate gate sizing from gate placement. 1
Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics
 Proc. ACM/IEEE Design Automation Conference, 2010
"... Abstract—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NPhard [1]. Several (suboptimal) gate sizing heuristics have been proposed over the past two decades, but research has su ..."
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Cited by 5 (3 self)
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Abstract—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NPhard [1]. Several (suboptimal) gate sizing heuristics have been proposed over the past two decades, but research has suffered from the lack of any systematic way of assessing the quality of the proposed algorithms. We develop a method to generate benchmark circuits (called eyecharts) of arbitrary size along with a method to compute their optimal solutions using dynamic programming. We evaluate the suboptimalities of some popular gate sizing algorithms. Eyecharts help diagnose the weaknesses of existing gate sizing algorithms, enable systematic and quantitative comparison of sizing algorithms, and catalyze further gate sizing research. Our results show that common sizing methods (including commercial tools) can be suboptimal by as much as 54 % (Vtassignment), 46 % (gate sizing) and 49 % (gatelength biasing) for realistic libraries and circuit topologies.
Complexity of Minimumdelay Gate Resizing
 In International Conference on VLSI Design
, 2001
"... Gate resizing for minimum circuit delay is a fundamental problem in the performance optimization of gatelevel circuits. In this paper, we study the complexity of two different minimumdelay gate resizing problems for combinational circuits composed of singleoutput gates. The first problem is that o ..."
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Cited by 3 (0 self)
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Gate resizing for minimum circuit delay is a fundamental problem in the performance optimization of gatelevel circuits. In this paper, we study the complexity of two different minimumdelay gate resizing problems for combinational circuits composed of singleoutput gates. The first problem is that of gate resizing for minimum circuit delay under the loaddependent delay model. The second problem is a variant of the first, where we relax the delay model to a loadindependent one, but impose load constraints instead, i.e., each gate output is not allowed to drive a capacitive load that exceeds its drive capacity. The goal, as before, is to minimize the delay through the circuit. To the best of our knowledge, there has been no published result on the complexity of these problems. In this paper, we prove that both problems are NPcomplete. The proofs are inspired by Murgai's work [6], in which the global fanout optimization problem under a fixed net topology was shown to be NPcomplete. These results, along with previously published ones, establish that gate resizing is a hard problem except under the most simplistic assumptions.
M.Pedram “Gate sizing with controlled Displacement
 in Proceedings of international symposium on physical design
"... Abstract In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively ident ..."
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Cited by 2 (1 self)
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Abstract In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and optimize the kmost critical paths in the circuit and their neighboring cells. All the operations are formulated and solved as mathematical programming problems by using efficient solution techniques. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches, which separate gate sizing from gate placement. 1
Upgrading Circuit Modules To Improve Performance
, 1991
"... We consider the problem of selectively upgrading some of the modules in a circuit so as to meet a specified performance level. The upgrading of a module involves replacing it with an equivalent module with zero delay (effectively) and this replacement has a cost or weight associated with. We show th ..."
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Cited by 2 (2 self)
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We consider the problem of selectively upgrading some of the modules in a circuit so as to meet a specified performance level. The upgrading of a module involves replacing it with an equivalent module with zero delay (effectively) and this replacement has a cost or weight associated with. We show that some versions of the minimum cost upgrading problem are NPhard while others are polynomially solvable. Several heuristics for the general problem are proposed and evaluated experimentally. Keywords And Phrases Module upgrading, performance, delay, complexity, NPhard, heuristics + This research was supported, in part, by the National Science Foundation under grant MIP8617374.  2  1. Introduction Often, a circuit can be modeled as a directed acyclic graph (dag) G in which there is a delay, d(v), associated with each vertex, v [CHAN90, GHAN87, MCGE90]. The dag vertices represent circuit modules while interconnects are modeled by dag edges. The delay, d(v), associated with vertex v of ...
On the Problem of Gate Assignment under Different Rise and Fall Delays
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2003
"... In most libraries, gate parameters such as the pintopin intrinsic delays, loaddependent coefficients, and input pin capacitances have different values for rising and falling signals. Most performance optimization algorithms, however, assume a single value for each parameter. ..."
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Cited by 1 (0 self)
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In most libraries, gate parameters such as the pintopin intrinsic delays, loaddependent coefficients, and input pin capacitances have different values for rising and falling signals. Most performance optimization algorithms, however, assume a single value for each parameter.