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12
system modeling for inverse problems
 IEEE Trans. Circuits Syst. I: Reg. Papers
, 2004
"... Abstract—Large disturbances in power systems often initiate complex interactions between continuous dynamics and discrete events. The paper develops a hybrid automaton that describes such behavior. Hybrid systems can be modeled in a systematic way by a set of differentialalgebraic equations, modifi ..."
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Cited by 13 (8 self)
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Abstract—Large disturbances in power systems often initiate complex interactions between continuous dynamics and discrete events. The paper develops a hybrid automaton that describes such behavior. Hybrid systems can be modeled in a systematic way by a set of differentialalgebraic equations, modified to incorporate impulse (state reset) action and constraint switching. This differentialalgebraic impulsiveswitched (DAIS) model is a realization of the hybrid automaton. The paper presents a practical objectoriented approach to implementing the DAIS model. Each component of a system is modeled autonomously. Connections between components are established by simple algebraic equations. The systematic nature of the DAIS model enables efficient computation of trajectory sensitivities, which in turn facilitate algorithms for solving inverse problems. The paper outlines a number of inverse problems, including parameter uncertainty, parameter estimation, grazing bifurcations, boundary value problems, and dynamic embedded optimization. Index Terms—Boundary value problems, dynamic embedded optimization, dynamic modeling, hybrid systems, inverse problems, power system dynamics. I.
Sensitivity, approximation and uncertainty in power system dynamic simulation
 IEEE TRANSACTIONS ON POWER SYSTEMS, SUBMITTED
, 2006
"... Parameters of power system models, in particular load models, are seldom known exactly. Yet dynamic security assessment relies upon simulation of those uncertain models. This paper proposes a computationally feasible approach to assessing the influence of uncertainty in simulations of power system d ..."
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Cited by 4 (3 self)
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Parameters of power system models, in particular load models, are seldom known exactly. Yet dynamic security assessment relies upon simulation of those uncertain models. This paper proposes a computationally feasible approach to assessing the influence of uncertainty in simulations of power system dynamic behaviour. It is shown that trajectory sensitivities can be used to generate accurate firstorder approximations of trajectories that arise from perturbed parameter sets. The computational cost of obtaining the sensitivities and perturbed trajectories is minimal. The mathematical structure of the trajectory approximations allows the effects of uncertainty to be quantified and visualized using worstcase analysis and probabilistic approaches.
Inverse Problems in Power Systems
"... Abstract — Large disturbances in power systems often initiate complex interactions between continuous dynamics and discrete events. Such behaviour can be modeled in a systematic way by a set of differentialalgebraic equations, modified to incorporate impulse (state reset) action and constraint swit ..."
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Cited by 1 (0 self)
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Abstract — Large disturbances in power systems often initiate complex interactions between continuous dynamics and discrete events. Such behaviour can be modeled in a systematic way by a set of differentialalgebraic equations, modified to incorporate impulse (state reset) action and constraint switching. The paper presents a practical objectoriented approach to implementing the DAIS model. The systematic nature of the DAIS model enables efficient computation of trajectory sensitivities, which in turn facilitate algorithms for solving inverse problems. The paper outlines a number of inverse problems, including parameter uncertainty, parameter estimation, boundary value problems, bordercollision bifurcations, locating critically stable trajectories, and optimal control.
Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing
"... Process variations play an increasingly important role on the success of analog circuits. Stateoftheart analog circuits are based on complex architectures and contain many hierarchical layers and parameters. Knowledge of the parameter variances and their contribution patterns is crucial for a suc ..."
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Cited by 1 (0 self)
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Process variations play an increasingly important role on the success of analog circuits. Stateoftheart analog circuits are based on complex architectures and contain many hierarchical layers and parameters. Knowledge of the parameter variances and their contribution patterns is crucial for a successful design process. This information is valuable to find solutions for many problems in design, design automation, testing, and fault tolerance. In this paper, we present a hierarchical variance analysis methodology for analog circuits. In the proposed method, we make use of previously computed values whenever possible so as to reduce computational time. Experimental results indicate that the proposed method provides both accuracy and computational efficiency when compared with prior approaches. 1.
DOI: 10.1155 Choice of a high level fault model for the Optimization of Validation Test Set reused for Manufacturing Test
, 2008
"... With the growing complexity of Wireless Systems on Chip integrating hundredofmillion transistors, electronic design methods need to be upgraded to reduce timetomarket. In this paper, the test benches defined for design validation or characterization of AMS & RF SoCs are optimized and reused ..."
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With the growing complexity of Wireless Systems on Chip integrating hundredofmillion transistors, electronic design methods need to be upgraded to reduce timetomarket. In this paper, the test benches defined for design validation or characterization of AMS & RF SoCs are optimized and reused for production testing. Although the original validation test set allows the verification of both design functionalities and performances, this test set is not well adapted to manufacturing test due to its high execution time and high test equipments costs requirement. The optimization of this validation test set is based on the evaluation of each test vector. This evaluation relies on high level fault modeling and fault simulation. Hence, a fault model based on the variations of the parameters of high abstraction level descriptions and its related qualification metric are presented. The choice of functional or behavioral abstraction levels is discussed by comparing their impact on structural fault coverage. Experiments are performed on the receiver part of a WCDMA transceiver. Results show that for this SoC, using behavioral abstraction level is justified for the generation of manufacturing test benches. I.
Qualification of Behavioral Level Design Validation
, 2008
"... The expansion of Wireless SystemsonChip leads to a rapid development of design and manufacturing methods. In this paper, the test vectors used for design validation of AMS & RF SoCs are evaluated and optimized. This qualification is based on a fault injection method. A fault model based on var ..."
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The expansion of Wireless SystemsonChip leads to a rapid development of design and manufacturing methods. In this paper, the test vectors used for design validation of AMS & RF SoCs are evaluated and optimized. This qualification is based on a fault injection method. A fault model based on variation of behavioral parameters and a related qualification metric are proposed. This approach is used in the receiver’s design of a WCDMA transceiver. A test set defined by verification engineers during the validation of this system is qualified and optimized. Then, this test set is compared with a second test set automatically generated by a developed tool.
Author manuscript, published in "IEEE Wireless Test Workhop (WTW07) (2007) 6267" Using of Behavioral level AMS & RF Simulation for Validation Test set Optimization
, 2008
"... The expansion of Wireless SystemsonChip leads to a rapid development of new design and test methods. In this paper, the test benches defined for design validation or characterization of AMS & RF SoCs are first optimized and then reused for production testing. Although the original validation ..."
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The expansion of Wireless SystemsonChip leads to a rapid development of new design and test methods. In this paper, the test benches defined for design validation or characterization of AMS & RF SoCs are first optimized and then reused for production testing. Although the original validation test set allows the verification of both design functionalities and performances, this test set is not well adapted to manufacturing test due to its high execution time and high test equipments costs requirement. The optimization of this validation set is based on the evaluation of each test stimuli. This evaluation relies on a high level faults simulation method. Hence, a fault model based on the variations of behavioral parameters and its related qualification metric are presented. This approach is used on the receiver part of a WCDMA transceiver. The test bench optimization realized is evaluated for manufacturing test thanks to structural fault coverage measurements. I.
Concurrent Detection of Erroneous Responses in Linear Analog Circuits
"... Abstract—This paper presents a novel methodology for concurrent error detection in linear analog circuits. The errordetection circuit monitors the input and some observable internal nodes of the examined circuit and generates an estimate of its output. The estimate coincides with the output in erro ..."
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Abstract—This paper presents a novel methodology for concurrent error detection in linear analog circuits. The errordetection circuit monitors the input and some observable internal nodes of the examined circuit and generates an estimate of its output. The estimate coincides with the output in errorfree operation, while in the presence of errors, it diverges. Thus, concurrent error detection is performed by comparing the two signals through an analog comparator. In essence, the errordetection circuit operates as a duplicate of the examined circuit, yet it is smaller, in general, and never exceeds the size of an actual duplicate. The proposed methodology is demonstrated on three analog filters. Index Terms—Analog test, concurrent error detection, linear analog circuits, state observation. I.
Concurrent Error Detection in Linear Analog Circuits Using State Estimation
"... We present a novel methodology for concurrent error detection in linear analog circuits. We develop a rigorous theory that yields an error detection circuit of size that is, in general, much smaller than a duplicate of the circuit under test. The error detection circuit monitors the input and some j ..."
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We present a novel methodology for concurrent error detection in linear analog circuits. We develop a rigorous theory that yields an error detection circuit of size that is, in general, much smaller than a duplicate of the circuit under test. The error detection circuit monitors the input and some judiciously selected observable internal nodes of the examined circuit to produce an estimate of its output. In errorfree operation, this estimate converges to the actual output value in a time interval that can be controlled to be sufficiently small. From then onwards, it follows exactly the output. The estimate is constructed such that it does not converge in the presence of errors and, thus, concurrent error detection is performed by comparing the two signals through an analog checker. The derived theory is validated through representative simulations on two filter examples. 1.
Statistical Analysis of Linear Analog Circuits Using Gaussian Message Passing in Factor Graphs
, 2009
"... This thesis introduces a novel application of factor graphs to the domain of analog circuits. It proposes a technique of leveraging factor graphs for performing statistical yield analysis of analog circuits that is much faster than the standard Monte Carlo/Simulation Program With Integrated Circuit ..."
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This thesis introduces a novel application of factor graphs to the domain of analog circuits. It proposes a technique of leveraging factor graphs for performing statistical yield analysis of analog circuits that is much faster than the standard Monte Carlo/Simulation Program With Integrated Circuit Emphasis (SPICE) simulation techniques. We have designed a tool chain to model an analog circuit and its corresponding factor graph and then use a Gaussian message passing approach along the edges of the graph for yield calculation. The tool is also capable of estimating unknown parameters of the circuit given known output statistics through backward message propagation in the factor graph. The tool builds upon the concept of domainspecific modeling leveraged for modeling and interpreting different kinds of analog circuits. Generic Modeling Environment (GME) is used to design modeling environment for analog circuits. It is a configurable tool set that supports creation of domainspecific design environments for different applications. This research has developed a generalized methodology that could be applied towards design automation of different kinds of analog circuits, both linear and nonlinear. The tool has been successfully used to model linear amplifier circuits and a nonlinear Metal Oxide Semiconductor Field Effect Transistor (MOSFET) circuit. The results obtained by Monte Carlo simulationsiv performed on these circuits are used as a reference in the project to compare against the tool’s results. The tool is tested for its efficiency in terms of time and accuracy against the standard results. (104 pages) To my loving family and friends.... v vi