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Structuring and Automating Hardware Proofs in a HigherOrder TheoremProving Environment
 Formal Methods in System Design
, 1993
"... . In this article we present a structured approach to formal hardware verification by modelling circuits at the registertransfer level using a restricted form of higherorder logic. This restricted form of higherorder logic is sufficient for obtaining succinct descriptions of hierarchically design ..."
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. In this article we present a structured approach to formal hardware verification by modelling circuits at the registertransfer level using a restricted form of higherorder logic. This restricted form of higherorder logic is sufficient for obtaining succinct descriptions of hierarchically designed registertransfer circuits. By exploiting the structure of the underlying hardware proofs and limiting the form of descriptions used, we have attained nearly complete automation in proving the equivalences of the specifications and implementations. A hardwarespecific tool called MEPHISTO converts the original goal into a set of simpler subgoals, which are then automatically solved by a generalpurpose, firstorder prover called FAUST. Furthermore, the complete verification framework is being integrated within a commercial VLSI CAD framework. Keywords: hardware verification, higherorder logic 1 Introduction The past decade has witnessed the spiralling of interest within the academic com...
Using PVS to Prove a Z Refinement: A Case Study
, 1997
"... The development of critical systems often places undue trust in the software tools used. This is especially true of compilers, which are a weak link between the source code produced and the ob ject code which is executed. Stepney [23] advocates a method for the production of trusted compilers (i.e. ..."
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Cited by 14 (5 self)
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The development of critical systems often places undue trust in the software tools used. This is especially true of compilers, which are a weak link between the source code produced and the ob ject code which is executed. Stepney [23] advocates a method for the production of trusted compilers (i.e. those which are guaranteed to produce ob ject code that is a correct refinement of the source code) by developing a proof of a small, but non trivial compiler by hand in the Z specification language. This approach is quick, but the type system of Z is too weak to ensure that partial functions are correctly applied. Here, we present a re{working of that development using the PVS specification and verification system. We describe the problems involved in translating from the partial set theory of Z to the total, higher order logic of the PVS system and the strengths and weaknesses of this approach.
A Verified Compiler for a Structured Assembly Language
 In proceedings of the 1991 international workshop on the HOL theorem Proving System and its applications. IEEE Computer
, 1991
"... We describe the verification of a compiler for a subset of the Vista language: a structured assembly language for the Viper microprocessor. This proof has been mechanically checked using the HOL system. We consider how the compiler correctness theorem could be used to deduce safety and liveness prop ..."
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We describe the verification of a compiler for a subset of the Vista language: a structured assembly language for the Viper microprocessor. This proof has been mechanically checked using the HOL system. We consider how the compiler correctness theorem could be used to deduce safety and liveness properties of compiled code from theorems stating that these properties hold of the source code. We also show how secure compilation can be achieved using automated theorem proving techniques. 1 Introduction In this paper, we describe the verification of a compiler for a subset of the Vista language[10]. Our motivation for verifying the compiler is to allow us to infer properties about the code which is actually executed from properties we prove about Vista programs. Previous work on the formal verification of compilers has largely considered the compiler correctness theorem itself to be the ultimate goal. Consequently, little attention has been given to identifying the way in which the correc...
Formal Verification of VIPER's ALU
, 1993
"... This research report describes the formal verification of an arithmetic logic unit of the VIPER microprocessor. VIPER is one of the first processors designed using formal methods. A formal model in HOL has been created which models the ALU at two levels: on the higher level, the ALU is specified as ..."
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This research report describes the formal verification of an arithmetic logic unit of the VIPER microprocessor. VIPER is one of the first processors designed using formal methods. A formal model in HOL has been created which models the ALU at two levels: on the higher level, the ALU is specified as a function taking two 32bit operands and returning a result; on the lower level, the ALU is implemented by a number of 4bit slices which should takes the same operands and returns the same result. The ALU is capable of performing thirteen different operations. A formal proof of functional equivalence of these two levels has been completed successfully. The complete HOL text of the ALU formal model and details of the proof procedures are included in this report. It has demonstrated that the HOL system is powerful and efficient enough to perform formal verification of realistic hardware design. 4 ALU Verification 1 Introduction This report describes the verification of the Arithmetic Logi...
From Formal Verification to Silicon Compilation
, 1991
"... Formal verification is emerging as a viable method for increasing design assurance for VLSI circuits. Potential benefits include reduction in the time and costs associated with testing and redesign, improved documentation and ease of modification, and greater confidence in the quality of the final p ..."
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Cited by 2 (0 self)
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Formal verification is emerging as a viable method for increasing design assurance for VLSI circuits. Potential benefits include reduction in the time and costs associated with testing and redesign, improved documentation and ease of modification, and greater confidence in the quality of the final product. This paper reports on an experiment whose main purpose was to identify the diculties of integrating formal verification with conventional VLSI CAD methodology. Our main conclusion is that the most effective use of formal hardware verification will be at the higher levels of VLSI system design, with lower levels best handled by conventional VLSI CAD tools.
Formal Specification and Verification for Critical Systems: Tools, Achievements, and Prospects
, 1991
"... Formal specification and verification use mathematical techniques to help document, specify, design, analyze, or certify computer software and hardware. Mathematicallybased notation can provide specifications that are precise and unambiguous and that can be checked mechanically for certain types ..."
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Formal specification and verification use mathematical techniques to help document, specify, design, analyze, or certify computer software and hardware. Mathematicallybased notation can provide specifications that are precise and unambiguous and that can be checked mechanically for certain types of error. Formal verification uses theorem proving techniques to establish consistency between one level of formal specification and another. This paper describes some of the issues in the design and use of formal specification languages and verification systems, outlines some examples of the application of formal methods to critical systems, and identifies the benefits that may be obtained from this technology. 1 Introduction Formal specification and verification are examples of what are often called formal methods in computer science. And formal methods are simply those that use mathematical techniques to help document, specify, design, analyze, or certify computer software and ha...
Theorem Provers of LCF
, 1997
"... This paper describes the core of an interactive theorem prover, "HOL Light", and a derivative work for the personal computer called "Diet HOL". This theorem prover descended from a line of theorem proving tools in a family of "LCFstyle" provers. This paper also explain ..."
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This paper describes the core of an interactive theorem prover, "HOL Light", and a derivative work for the personal computer called "Diet HOL". This theorem prover descended from a line of theorem proving tools in a family of "LCFstyle" provers. This paper also explains these terms, outlines some of the basic features of this family of tools, and introduces the important provers in this class. 1 Introduction Theorem provers are some of the most popular formal methods tools. While they may include many features, at the very least they consist of a specification language (usually based on some type of formal logic), and an inference engine which transforms logical terms according to wellknown rules of deduction. Users prove theorems by making definitions or assertions which describe their problem as well as a solution, then use the inference procedures to prove properties of their solution. Theorem provers have been used in academia to verify software ([Joy89] [Moo88] [BW97]) and ha...
A Programming Logic for a Verified Structured Assembly Language
, 1992
"... We describe a derived programming logic for a generic structured assembly language. It has been combined with a compiler correctness theorem. This allows us to deduce correctness properties of object code from corresponding properties of the source code proved with the programming logic. All proofs ..."
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We describe a derived programming logic for a generic structured assembly language. It has been combined with a compiler correctness theorem. This allows us to deduce correctness properties of object code from corresponding properties of the source code proved with the programming logic. All proofs have been carried out using the HOL system.