Silicon integrated circuit spiral inductors and transformers are analyzed using electromagnetic analysis. With appropriate approximations, the calculations are reduced to electrostatic and magnetostatic calculations. The important effects of substrate loss are included in the analysis. Classic circuit analysis and network analysis techniques are used to derive two-port parameters from the circuits. From two-port measurements, loworder, frequency-independent lumped circuits are used to model the physical behavior over a broad-frequency range. The analysis is applied to traditional square and polygon inductors and transformer structures as well as to multilayer metal structures and coupled inductors. A custom computer-aided-design tool called ASITIC is described, which is used for the analysis, design, and optimization of these structures. Measurements taken over a frequency range from 100 MHz to 5 GHz show good agreement with theory.

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Abstract—In this paper, a closed-form integral representation for the eddy-current losses over a conductive substrate is presented. The results are applicable to monolithic inductors and transformers, especially when such structures are realized over an epitaxial CMOS substrate. The technique is verified against measured results from 100 MHz to 14 GHz for spiral inductors. Index Terms—CMOS substrate losses, eddy currents, monolithic inductors, monolithic transformers, spiral inductors, spiral transformers. I.

The unprecedented impact of noise coupling on Mixed-Signal Systems-On-a-Chip (MS-SOC) functionality, brings a new set of challenges for Electronics Design Automation (EDA) tool developers. In this paper, we propose a new approach which combines a thorough physical comprehension of the noise coupling effects with an improved Boundary-Element-Method (BEM) to matrix storage. The low computational efforts required, as well as speed and accuracy reached, makes this method a highly promising alternative to verify complex MS-SOCs.

Abstract: The relentless move toward single chip integration of RF, analog and digital blocks results in significant noise coupling effects that can degrade performance and hence, should be controlled. In this paper, we propose a practical methodology that uses a suite of commercial tools in combination with a high-speed extractor based on an innovative semi-analytical method to deal with noise coupling problems, and enable RF designers to achieve a first silicon-success of their chips. The integration of the methodology in a typical RF design flow is illustrated and its successful application to achieve a singlechip integration of a transceiver demonstrated. The proliferation of Mixed-Signal-SOCs leads to two seemingly contradictory requirements on design methodology: on one hand, higher levels abstraction is needed to cope with the added complexity in design, while at the same time, the shrinking process technologies

Abstract—Continual scaling of transistors and interconnects has exacerbated the power and thermal management problems in the design of ultralarge-scale integrated (ULSI) circuits. This paper presents an efficient thermal-analysis method of O(N lg N) complexity, where N is the number of blocks that discretize the heat-source or temperature-observation regions. The method is named LOTAGre and formulated using the Green’s function for heat conduction through multiple-layer materials, which account for the structure of ULSI chips and the accompanying heat sinks and mounting accessories. In addition to analyzing the thermal effects of the distributive heat sources, LOTAGre also considers the ambient temperature effects that are generally excluded in conventional Green’s function-based thermal-analysis tools in order to avoid the concomitant analytical complexity. By employing the well-known eigen-expansion technique and classical transmissionline theory, fully analytical and explicit formulas are derived in this paper for the multilayer Green’s function with the inclusion of the s-domain version, the homogeneous and inhomogeneous solutions to the heat-conduction equation. Then, the discrete cosine transform and its inversion are employed to accelerate the numerical computation of the homogeneous and inhomogeneous solutions. This paper includes extensive experimental results to demonstrate that LOTAGre can be as accurate as FLUENT, a sophisticated computational fluid dynamics tool, while speeding up the simulation run time by two to three orders of magnitude in comparison to FLUENT as well as conventional Green’s functionbased thermal-analysis methods. This paper also discusses the limitations of using the traditional single-layer thermal model in thermal analysis for approximating a multilayer chip structure. Index Terms—Algorithms, discrete cosine transforms, distributed parameter circuits, electrothermal effects, Green’s function, temperature. I.

Noise caused by the activity of integrated circuits is a limiting factor for the development of future VLSI circuits. Transients of voltages and currents couple perturbations to the co-integrated circuits where the most effective medium to propagate noise is the silicon substrate. The effect is especially important where high-speed digital circuits are integrated together with highly sensitive analog sections, which is the case of modern communication transceivers. Taking into account the effect of noise during the circuit design requires a fine electrical modeling of the substrate and noise generation. The capability of substrate to propagate signals from DC to very high frequencies has to be understood and modeled, together with the role of doping profile and topology of doped regions (layout). In this tutorial paper the sources, propagation of noise and sensitivity of MOS circuits are presented and its trend in the next technology generations is evaluated. The challenges that modeling techniques and CAD tools have to face are commented, and the key points and more likely solutions are discussed.

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There are more and more System-on-a-Chip (SoC) products available these days. However, in SoC applications it is always a challenge to integrate sensitive components with noisy digital blocks on the same chip. The results of our research indicate there are several digital parameters significant to substrate crosstalk. Based on the study, we propose a digital block to characterize analog blocks, and use a synthesized PLL as the test vehicle to verify the proposal. This research first reviews measurements from an IEEE 802.11a wireless LAN baseband/MAC processor. Results confirm that there are dominant components of digital switching noise spectra, predetermined by the architecture. Based on this observation and supporting work at Stanford, a new low-complexity Digital Noise Emulator (DNE) is presented which emulates global digital signatures of complicated digital systems. The DNE can generate both deterministic and random signals, and inject different amounts of digital noise into the substrate for further studies. The work also covers measurement results from a test chip including a DNE and ring-oscillator based PLL. The DNE test-chip was fabricated using a TSMC 0.18µm CL018G technology. Measurement results reveal that there are several digital parameters, including phase and frequency, important to PLL performance. By properly controlling the phase of digital inputs with respect to the PLL reference clock, improvements up to 71% reduction in jitter standard deviation from the worst case relative to best case can be observed. In addition, the measurement data at representative DNE operating frequencies are presented. Experiment results also confirm that deterministic and random noise will have different impact on performance. Finally, it is demonstrated that the DNE can be used for noise cancellation to improve system performance. By activating a DNE, an impact to the target PLL caused by a second noise source is minimized. A 50% reduction in jitter standard deviation was obtained in the case of canceling deterministic noise.

Due to the roaring power dissipation and gaining popularity of 3D integration, thermal dissipation has been a critical concern of modern VLSI design. The availability for chip-level 3D thermal analysis is crucial for thermal integrity analysis. In this paper, we formulated an analytical Green function solution of the 3D temperature distribution in a multi-layer integrated circuit substrate. The proposed analytical solution differs from the previously reported results in two ways: (a) This is a 3D temperature distribution solution, while only 2D solutions are reported in the past; and (b) a rectangular coordinate system is used rather than the cylindrical coordinates used in the past which leads to a more proper and accurate representation to the VLSI geometry. Experimental results demonstrate the speed advantage of our approach and the accuracy within the error 0.5 % when compared with commercial computational fluid dynamics software ANSYS [13].