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48
DAGaware AIG rewriting: A fresh look at combinational logic synthesis
 In DAC ’06: Proceedings of the 43rd annual conference on Design automation
, 2006
"... This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using AndInverter Graphs (AIGs), the networks of twoinput ANDs and inverters. The optimization works by alternating DAGaware AIG rew ..."
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Cited by 84 (32 self)
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This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using AndInverter Graphs (AIGs), the networks of twoinput ANDs and inverters. The optimization works by alternating DAGaware AIG rewriting, which reduces area by sharing common logic without increasing delay, and algebraic AIG balancing, which minimizes delay without increasing area. The new technologyindependent flow is implemented in a publicdomain tool ABC. Experiments on large industrial benchmarks show that the proposed methodology scales to very large designs and is several orders of magnitude faster than SIS and MVSIS while offering comparable or better quality when measured by the quality of the network after mapping. 1
Improvements to Technology Mapping for LUTbased FPGAs
 IEEE TCAD
, 2007
"... The paper presents several improvements to stateoftheart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improved cut enumeration computes all Kfeasible cuts without pruning for up to 7 inputs for the largest MCNC benchmarks. A new t ..."
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Cited by 32 (12 self)
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The paper presents several improvements to stateoftheart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improved cut enumeration computes all Kfeasible cuts without pruning for up to 7 inputs for the largest MCNC benchmarks. A new technique for onthefly cut dropping reduces by orders of magnitude memory needed to represent cuts for large designs. Improved area recovery leads to mappings with area on average 7% smaller than DAOmap, while preserving delay optimality when starting from the same optimized netlists. Applying mapping with structural choices derived by a synthesis flow on average reduces delay by 7 % and area by 14%, compared to DAOmap.
ABC: An Academic IndustrialStrength Verification Tool
"... Abstract. ABC is a publicdomain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transformations based on AndInverter Graphs (AIGs), with a variety of innovative algorithms. A focus on the synergy of ..."
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Cited by 30 (13 self)
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Abstract. ABC is a publicdomain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transformations based on AndInverter Graphs (AIGs), with a variety of innovative algorithms. A focus on the synergy of sequential synthesis and sequential verification leads to improvements in both domains. This paper introduces ABC, motivates its development, and illustrates its use in formal verification.
Scalable and scalablyverifiable sequential synthesis
 Proc. ICCAD'08. http://www.eecs.berkeley.edu/~alanmi/publications/2008/iccad08_se q.pdf A. Mishchenko
"... This paper describes an efficient implementation of sequential synthesis that uses induction to detect and merge sequentiallyequivalent nodes. Stateencoding, scan chains, and test vectors are essentially preserved. Moreover, the sequential synthesis results are sequentially verifiable using an inde ..."
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Cited by 18 (14 self)
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This paper describes an efficient implementation of sequential synthesis that uses induction to detect and merge sequentiallyequivalent nodes. Stateencoding, scan chains, and test vectors are essentially preserved. Moreover, the sequential synthesis results are sequentially verifiable using an independent inductive prover similar to that used for synthesis, with guaranteed completeness. Experiments with this sequential synthesis show effectiveness. When applied to a set of 20 industrial benchmarks ranging up to 26K registers and up to 53K 6LUTs, average reductions in register and area are 12.9 % and 13.1 % respectively while delay is reduced by 1.4%. When applied to the largest academic benchmarks, an average reduction in both registers and area is more than 30%. The associated sequential verification is also scalable and runs about 2x slower than synthesis. The implementation is available in the synthesis and verification system ABC. 1
SATbased logic optimization and resynthesis
 Proc. IWLS '07
"... The paper develops a technologyindependent optimization and postmapping resynthesis for combinational logic networks, with emphasis on scalability and efficient implementation. The proposed resynthesis (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of opt ..."
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Cited by 9 (7 self)
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The paper develops a technologyindependent optimization and postmapping resynthesis for combinational logic networks, with emphasis on scalability and efficient implementation. The proposed resynthesis (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of optimization tasks, and (c) has reasonable runtime on large industrial designs. The approach is based on several heterogeneous algorithms, which include structural analysis, random and constrained simulation, and manipulation of Boolean functions using a SAT solver. Structural methods include improved windowing, which focuses on reconvergent logic structures rich in functional flexibilities. An efficient simulation scheme is used for fast filtering of infeasible resubstitution candidates. Finally, it is shown how a mainstream SAT solver can be minimally modified to combine it with an interpolation package, which computes Boolean functions of nodes after resynthesis as a byproduct of completed feasibility proofs. Experimental results, focused on minimizing the number of nets after FPGA mapping, demonstrate that the proposed resynthesis, applied to 20 highly optimized and mapped industrial designs, achieve the following additional reductions: 4.9 % in LUT count, 14.0 % in levels, and 5.5 % in net count. 1
Symmetry detection for large boolean functions using circuit representation, simulation and satisfiability
 in DAC
, 2006
"... Classical twovariable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuitbased method that makes uses of structural analysis, integrated simulation and Boolean satisfiability for fast and scalable d ..."
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Cited by 9 (2 self)
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Classical twovariable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuitbased method that makes uses of structural analysis, integrated simulation and Boolean satisfiability for fast and scalable detection of classical symmetries of completelyspecified Boolean functions. This is in contrast to previous incomplete circuitbased methods and complete BDDbased methods. Experimental results demonstrate that the proposed method works for large Boolean functions, for which BDDs cannot be constructed.
Boolean factoring and decomposition of logic networks
 in ICCAD
, 2008
"... This paper presents new methods for restructuring logic networks based on fast Boolean techniques. The basis for these are 1) a cutbased view of a logic network, 2) exploiting the uniqueness and speed of disjointsupport decompositions, 3) a new heuristic for speeding these up, 4) extending these t ..."
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Cited by 7 (3 self)
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This paper presents new methods for restructuring logic networks based on fast Boolean techniques. The basis for these are 1) a cutbased view of a logic network, 2) exploiting the uniqueness and speed of disjointsupport decompositions, 3) a new heuristic for speeding these up, 4) extending these to general decompositions, and 5) limiting local transformations to functions with 16 or less inputs so that fast truth table manipulations can be used in all operations. Boolean methods lessen the structural bias of algebraic methods, while still allowing for high speed and multiple iterations. Experimental results on KLUT networks show an average additional reduction of 5.4 % in LUT count, while preserving delay, compared to heavily optimized versions of the same networks. 1
Stepping forward with interpolants in unbounded model checking
 In Proc. ICCAD’06
, 2006
"... This paper addresses SATbased Unbounded Model Checking based on Craig Interpolants. This recently introduced methodology is often able to outperform BDDs and other SATbased techniques on large verification instances. Based on refutation proofs generated by SAT solvers, interpolants provide compact ..."
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Cited by 7 (0 self)
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This paper addresses SATbased Unbounded Model Checking based on Craig Interpolants. This recently introduced methodology is often able to outperform BDDs and other SATbased techniques on large verification instances. Based on refutation proofs generated by SAT solvers, interpolants provide compact circuit representations of state sets, and abstract away several details non relevant for proofs. We propose three main contributions, aimed at controlling interpolant size and traversal depth. First of all, we introduce interpolantbased dynamic abstraction to reduce the support of the computed interpolant. Second, we propose new advances in interpolant compaction by redundancy removal. Both techniques rely on an effective application of the incremental SAT paradigm. Finally, we also introduce interpolant computation exploiting circuit quantification, instead of SAT refutation proofs. Experimental results are specifically oriented to prove properties, rather than disproving them (bug hunting). They show how the methodology is able to extend the applicability of interpolant based Model Checking to larger and deeper verification instances. 1.
Scalable don'tcarebased logic optimization and resynthesis
 Proc. FPGA '09
"... We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of optimization tasks, and (c) has reason ..."
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Cited by 6 (2 self)
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We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of optimization tasks, and (c) has reasonable runtime on industrial designs. The approach uses don’t cares computed for a window surrounding a node and can take into account external don’t cares (e.g. unreachable states). It uses a SAT solver and interpolation to find a new representation for a node. This representation can be in terms of inputs from other nodes in the window thus effecting Boolean resubstitution. Experimental results on 6input LUT networks after high effort synthesis show substantial reductions in area and delay. When applied to 20 large academic benchmarks, the LUT count and logic level is reduced by 45.0 % and 12.2%, respectively. The longest runtime for synthesis and mapping is about two minutes. When applied to a set of 14 industrial benchmarks ranging up to 83K 6LUTs, the LUT count and logic level is reduced by 11.8 % and 16.5%, respectively. Experimental results on 6input LUT networks after higheffort synthesis show substantial reductions in area and delay. The longest runtime is about 30 minutes.
Automated Design Debugging with Maximum Satisfiability
"... As contemporary VLSI designs grow in complexity, design debugging has rapidly established itself as one of the largest bottlenecks in the design cycle today. Automated debug solutions such as those based on Boolean Satisfiability (SAT) enable engineers to reduce the debug effort by localizing possib ..."
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Cited by 6 (3 self)
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As contemporary VLSI designs grow in complexity, design debugging has rapidly established itself as one of the largest bottlenecks in the design cycle today. Automated debug solutions such as those based on Boolean Satisfiability (SAT) enable engineers to reduce the debug effort by localizing possible error sources in the design. Unfortunately, adaptation of these techniques to industrial designs is still limited by the performance and capacity of the underlying engines. This paper presents a novel formulation of the debugging problem using MaxSat to improve the performance and applicability of automated debuggers. Our technique not only identifies errors in the design but also indicates when the bug is excited in the error trace. MaxSat allows for a simpler formulation of the debugging problem, reducing the problem size by 80 % compared to a conventional SATbased technique. Empirical results demonstrate the effectiveness of the proposed formulation as runtime improvements of 4.5× are observed on average. This work introduces two performance improvements to further reduce the time required to find all error sources within the design by an order of magnitude.