technique for low-power operational amplifiers is presented in this paper. With an active-feedback mechanism, a high-speed block separates the low-frequency high-gain path and high-frequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier. The gain stage in the active-feedback network also reduces the size of the compensation capacitors such that the overall chip area of the amplifier becomes smaller and the slew rate is improved. Furthermore, the presence of a left-half-plane zero in the proposed AFFC topology improves the stability and settling behavior of the amplifier. Three-stage amplifiers based on AFFC and nested-Miller compensation (NMC) techniques have been implemented by a commercial 0.8- m CMOS process. When driving a 120-pF capacitive load, the AFFC amplifier achieves over 100-dB dc gain, 4.5-MHz gain-bandwidth product (GBW) , 65 phase margin, and 1.5-V / s average slew rate, while only dissipating 400- W power at a 2-V supply. Compared to a three-stage NMC amplifier, the proposed AFFC amplifier provides improvement in both the GBW and slew rate by 11 times and reduces the chip area by 2.3 times without significant increase in the power consumption. Index Terms—Active feedback, active-capacitive-feedback network, amplifiers, frequency compensation, multistage amplifiers.

Abstract—A dual-path amplifier topology with dual-loop parallel compensation technique is proposed for low-power three-stage amplifiers. By using two parallel high-speed paths for high-frequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both the bandwidth and slew rate are thus significantly improved. Implemented in a 0.6- m CMOS process, the proposed three-stage amplifier has over 100-dB gain, 7-MHz gain-bandwidth product, and 3.3-V / s average slew rate while only dissipating 330 W at 1.5 V, when driving a 25-k //120-pF load. The proposed amplifier achieves at least two times improvement in bandwidth-to-power and slew-rate-to-power efficiencies than all other reported multistage amplifiers using different compensation topologies. Index Terms—Amplifiers, dual loop, dual path, frequency compensation, multistage amplifiers. I.

Abstract—This paper presents a low-power stability strategy to significantly reduce the power consumption of a three-stage amplifier using active-feedback frequency compensation (AFFC). The bandwidth of the amplifier can also be enhanced. Simulation results verify that the power dissipation of the AFFC amplifier is reduced by 43 % and the bandwidth is improved by 32.5 % by using the proposed stability strategy. In addition, a dynamic feedforward stage (DFS), which can be embedded into the AFFC amplifier to improve the transient responses without consuming extra power, is proposed. Implemented in a 0.6- m CMOS process, experimental results show that both AFFC amplifiers with and without DFS achieve almost the same small-signal performances while the amplifier with DFS improves both the negative slew rate and negative 1 % settling time by two times. Index Terms—Active feedback, amplifiers, dynamic feedforward stage (DFS), frequency compensation, low-power stability strategy, multistage amplifiers. I.