Growth of distributed systems has attained unstoppable momentum. If we better understood how to think about, analyze, and design distributed systems, we could direct their implementation with more confidence.

This paper extends earlier research on hash-join algorithms to a multiprocessor architecture. Implementations of a number of centralized join algorithms are described and measured. Evaluation of these algorithms served to verify earlier analytical results. In addition, they demonstrate that bit vector filtering provides dramatic improvement in the performance of all algorithms including the sort merge join algorithm. Multiprocessor configurations of the centralized Grace and Hybrid hash-join algorithms are also presented. Both algorithms are shown to provide linear increases in throughput with corresponding increases in processor and disk resources. 1.

A Hierarchy of Processor-And-Memory #HPAM# can be viewed as an extension of the notion of a memory hierarchy. The extension entails the inclusion of processors with di#erent performance in di#erent levels of the memory hierarchy. Technology trends, applications behavior and previous research suggest that a multiprocessor system organized as a Hierarchy of Processor-And-Memory may o#er considerable advantages over conventional multiprocessor organizations. This paper quanti#es and analyzes the advantages of computing-in-memory, for a multi-level HPAM system, as comparedtoaconventional multiprocessor system with the same cost. The analysis entails using performancemodels and simulation data. Underlying the comparative study is the assumption that the cost of a processor is in proportion to the squareof its performance. The 9 benchmarks used in the evaluations belong to the CMU, Perfect Benchmarks and SPEC95 suites. While the evaluation methodology takes into account the heterogeneity of HPAM, the emphasis is placedonmodeling the impact of computingin -memory on the relative performance of the multiprocessors under study. The results indicate that, with rare exceptions, HPAM outperforms conventional multiprocessor designs of identical cost by as much a 80# in the benchmarks and the ranges of model parameters considered in the study. In the very few exceptions to this conclusion HPAM is never outperformed by more than 20#.

ABSTRACT-The importance of reducing processor-memory bandwidth is recognized in two distinct situa-tions: single board computer systems and microproces-sors of the future. Cache memory is investigated as a way to reduce the memory-processor traffic. We show that traditional caches which depend heavily on spatial locality (look-ahead) for their performance are inap-propriate in these environments because they generate large bursts of bus traffic. A cache exploiting primarily temporal locality (look-behind) is then proposed and demonstrated to be effective in an environment where process switches are infrequent. We argue that such an environment is possible if the traffic to backing store is small enough that many processors can share a common memory and if the cache data consistency problem is solved. We demonstrate that such a cache can indeed reduce traffic to memory greatly, and introduce e.r elegant solution to the cache coherency problem. 1.