Future multicores will be very complex: at the very least, they may contain statically heterogeneous cores, which are designed with different engineering trade-offs, and dynamically heterogeneous cores, which have different, and rapidly changing, execution characteristics. Hardware companies traditionally expose chips to system software at a very low level, effectively saying, “Here is what we built, now do something with it.” However, there are several advantages to having the chip itself manage these emerging complexities, while exposing a more generic interface to software. We do not have all of the answers for the appropriate role of system software, but we do suggest that system architects should carefully consider the benefits of abstraction when designing future systems.

Power has become a primary concern for HPC systems. Dynamic voltage and frequency scaling (DVFS) and dynamic concurrency throttling (DCT) are two software tools (or knobs) for reducing the dynamic power consumption of HPC systems. To date, few works have considered the synergistic integration of DVFS and DCT in performance-constrained systems, and, to the best of our knowledge, no prior research has developed application-aware simultaneous DVFS and DCT controllers in real systems and parallel programming frameworks. We present a multi-dimensional, online performance prediction framework, which we deploy to address the problem of simultaneous runtime optimization of DVFS and DCT on multi-core systems. We present results from an implementation of the prediction framework in a runtime system linked to the Intel OpenMP runtime environment and running on a real dual-processor quad-core system. We show that the prediction framework derives near-optimal settings of the power-aware program adaptation knobs that we consider. Our overall runtime optimization framework achieves significant reductions in energy (19 % mean) and ED 2 (40 % mean), through simultaneous power savings (6 % mean) and performance improvements (14 % mean). Our prediction and adaptation framework outperforms earlier solutions that adapt only DVFS or DCT, as well as one that sequentially applies DCT then DVFS. Further, our results indicate that prediction-based schemes for runtime adaptation compare favorably and typically improve upon heuristic search-based approaches in both performance and energy savings.

As the computing industry enters the multicore era, exponential growth in the number of transistors on a chip continues to present challenges and opportunities to computer architects. This dissertation identifies and addresses one emerging issue in particular: that of dynamic heterogeneity, which can arise, even among physically homogeneous cores, from changing reliability, power, or thermal conditions, or different cache and TLB contents. This heterogeneity greatly complicates software’s traditional task of assigning computation to cores because the conditions can change more rapidly than software can adapt. This dissertation begins a push toward hardware taking a more active role in the management of its computation resources. This dissertation proposes hardware techniques to virtualize the cores of a multicore processor, allowing hardware to transparently remap any number of the virtual processors exposed even to a single operating system to any subset of physical cores. Multicore virtualization operates with minimal overhead, and is shown to enable three novel resource management applications. In the first

Although transistor density continues to increase, voltage scaling has stalled and thus power density is increasing each technology generation. Particularly in mobile devices, which have limited cooling options, these trends lead to a utilization wall in which sustained chip performance is limited primarily by power rather than area. However, many mobile applications do not demand sustained performance; rather they comprise short bursts of computation in response to sporadic user activity. To improve responsiveness for such applications, this paper explores activating otherwise powered-down cores for sub-second bursts of intense parallel computation. The approach exploits the concept of computational sprinting, in which a chip temporarily exceeds its sustainable thermal power budget to provide instantaneous throughput, after which the chip must return to nominal operation to cool down. To demonstrate the feasibility of this approach, we analyze the thermal and electrical characteristics of a smart-phone-like system that nominally operates a single core (∼1W peak), but can sprint with up to 16 cores for hundreds of milliseconds. We describe a thermal design that incorporates phase-change materials to provide thermal capacitance to enable such sprints. We analyze image recognition kernels to show that parallel sprinting has the potential to achieve the task response time of a 16W chip within the thermal constraints of a 1W mobile platform. 1.