Abstract | The impact of CMOS technology scaling on power consumption in analog circuits was examined. For high-resolution, high-speed, switched-capacitor circuits, it was found that through careful scaling of gate voltage bias V gs,Vt with channel length L, substantial power scaling can be achieved. For low-power applications, it is important to optimize V gs, Vt for a given technology. It is also shown that sub-threshold conduction presents a fundamental limit to power scaling for class A circuits. I.