Abstract. Writing an optimizing back end is expensive, in part because it requires mastery of both a target machine and a compiler’s internals. We separate these concerns by isolating target-machine knowledge in declarative machine descriptions. We then analyze these descriptions to automatically generate machinespecific components of the back end. In this work, we generate a recognizer; this component, which identifies register transfers that correspond to target-machine instructions, plays a key role in instruction selection in such compilers as vpo, gcc and Quick C--. We present analyses and transformations that address the major challenge in generating a recognizer: accounting for compile-time abstractions not present in a machine description, including variables, pseudo-registers, stack slots, and labels. 1

transPROSE is a comprehensive research project investigating techniques for transporting programs securely over potentially insecure channels. The central focus of this project is the development of a blueprint for a nextgeneration mobile-code distribution format. A problem of previous approaches to mobile-code security has been that the additional provisions for security lead to a loss of efficiency, often to the extent of making an otherwise virtuous security scheme unusable for all but trivial programs. Project transPROSE strives to deviate from the common approach of studying security in isolation and instead focuses simultaneously on multiple aspects of mobile-code quality. Besides security, such aspects include encoding density, speed of dynamic code generation, and the eventual execution performance. This paper gives a high-level overview of project transPROSE and presents initial results.

Building compilers that generate correct code is difficult. In this paper we present a compiler testing technique that closes the gap between actual compiler implementations and correct compilers. Using formal specifications of procedure calling conventions, we have built a target-sensitive test suite generator that builds test cases for a specific aspect of compiler code generators: the procedure calling sequence generator. By exercising compilers with these target-specific test suites, our automated testing tool has exposed bugs in every compiler tested. These compilers include ones that have been in heavy use for many years. The detected bugs cause more than 14,000 test cases to fail.

Software designers face many challenges when developing applications for embedded systems. One major challenge is meeting the conflicting constraints of speed, code size and power consumption. Embedded application developers often resort to hand-coded assembly language to meet these constraints since traditional optimizing compiler technology is usually of little help in addressing this challenge. The results are software systems that are not portable, less robust and more costly to develop and maintain. Another limitation is that compilers traditionally apply the optimizations to a program in a fixed order. However, it has long been known that a single ordering of optimization phases will not produce the best code for every application. In fact, the smallest unit of compilation in most compilers is typically a function and the programmer has no control over the code improvement process other than setting flags to enable or disable certain optimization phases. This paper describes a new code improvement paradigm implemented in a system called VISTA that can help achieve the cost/performance trade-offs that embedded applications demand. The VISTA system opens the code improvement process and gives the application programmer, when necessary, the ability to finely control it. VISTA also provides support for finding effective sequences of optimization phases. This support includes the ability to interactively get

We are using ML to build a compiler that does low-level optimization. To support optimizations in classic imperative style, we built a control-flow graph using mutable pointers and other mutable state in the nodes. This decision proved unfortunate: the mutable flow graph was big and complex, and it led to many bugs. We have replaced it by a smaller, simpler, applicative flow graph based on Huet’s (1997) zipper. The new flow graph is a success; this paper presents its design and shows how it leads to a gratifyingly simple implementation of the dataflow framework developed by Lerner, Grove, and Chambers (2002). 1

In an era of rapid design of microprocessors for desktop systems, embedded systems, and handheld computing devices, the timely construction of systems software is essential. Systems software, such as assemblers, compilers, and debuggers, must be constructed before development of application software for a microprocessor can commence. However, the implementation of such machine-specific applications is difficult and time consuming. Therefore, to remain competitive, it is imperative that systems software designs focus on portability to reduce implementation time and ensure rapid delivery of complete systems to the market. This dissertation presents the Computing System Description Language (CSDL) framework that addresses these rapid development requirements. We illustrate the CSDL framework by developing an instruction-set description component (RTL), an optional procedure calling convention description component (CCL), and the mechanism we use to extend extant descriptions (CSDL). RTL and its accompanying microinstruction descriptions (RTL) further the state-of-the-art in specifying semantics of machine instructions. RTL adds a new type system and abstract syntax that facilitates more accurate specification and automatic detection of errors by RTL manipulators. RTL machine descriptions are also application independent---they completely separate the specification of semantics from the application's implementation. The CCL specification language is the first work to formally describe procedure calling conventions. We demonstrate two distinct uses for CCL descriptions: code generation and fault detection. Using CCL we have built compilers that are more robust, and found and diagnosed faults in production compilers. CCL, RTL, and RTL descriptions are bound together u...

: Many modern code generation methods use tree pattern matching with dynamic programming. However, especially in the case of an irregular special-purpose processor architecture their lack of transparency and stability may be problematic: it is difficult to predict the exact code generation result in advance, and the effects of a modification in the code generation rules may be surprisingly wide. In contrast, macro expansion techniques are intuitively transparent. When global variables are disallowed, macro expansion typically has the Church-Rosser property: the final expansion result is independent of the expansion order of the individual intermediate macro calls. Besides enabling parallel implementation, order-independence means stability: the effects of modifying a macro definition are guaranteed to remain local. The locality is actually the problem with macro expansion; code optimization is improved when an assembly language macro is sensitive to its context. For instance, it should...

Applications in embedded systems often need to meet specified timing constraints. It is advantageous to not only calculate the Worst-Case Execution Time (WCET) of an application, but to also perform transformations which reduce the WCET since an application with a lower WCET will be less likely to violate its timing constraints. Some processors incur a pipeline delay whenever an instruction transfers control to a target that is not the next sequential instruction. Code positioning optimizations attempt to reduce these delays by positioning the basic blocks to minimize the number of unconditional jumps and taken conditional branches that occur. Traditional code positioning algorithms use profile data to find the frequently executed edges between basic blocks, then minimize the transfers of control along these edges to reduce the Average Case Execution Time (ACET). This paper introduces a WCET code positioning optimization, driven by the worst-case (WC) path information from a timing analyzer, to reduce the WCET instead of ACET. This WCET optimization changes the layout of the code in memory to reduce the branch penalties along the WC paths. Unlike the frequency of edges in traditional profile-driven code positioning, the WC path may change after code positioning decisions are made. Thus, WCET code positioning is inherently more challenging than ACET code positioning. The experimental results show that this optimization typically finds the optimal layout of the basic blocks with the minimal WCET. The results show over a 7 % reduction in WCET is achieved after code positioning is performed.

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this paper, we describe the only known formal model and specification language for procedure calling conventions. The model and language, in combination, facilitate the accurate specification of conventions that can be shown to be both consistent and complete. Further, we show how the convention specifications can be used to automatically generate that part of the code generator responsible for generating procedure calls. Finally, we discuss a new compiler testing technique that uses the specifications to further close the gap between actual compiler implementations and correct compilers. The technique, which uses a target-sensitive test suite generator, has exposed and diagnosed faults in several C compilers.