With the ever-increasing performance and power savings needed by embedded systems, it is clear that new architectural solutions are required. Exploring the inherent parallelism available in the applications may seem to be a natural solution, but what should be done when parallelism is limited? One alternative is to accelerate the sequential instruction flow execution paradigm, trading sequential logic by combinational logic. In this paper, this is explored coupling a coarse-grained reconfigurable array with an embedded processor through a technique called Dynamic Instruction Merging. This mechanism detects sequences of data-dependent instructions on-the-fly, and dynamically transfers their execution to a more efficient engine: a coarse-grained array. The technique is proven effective even for programs with low explicit parallelism, and full software compatibility is maintained. The goal of this work is to analyze the cost of implementing such a scheme by varying the size of the array and the cache responsible for storing its configuration. It is shown that the implementation is possible enabling mean performance increases of up to 2.8 times, and energy savings of up to 46 % when using the SPECjvm981 benchmarks.