A CMOS 64 # 64 pixel area image sensor chip using Sigma-Delta modulation at each pixel for A#D conversion is described. The image data output is digital. The chip was fabricated using a 1.2#mtwo layer metal single layer poly n-well CMOS process. Each pixel block consists of a phototransistor and 22 MOS transistors. Test results demonstrate a dynamic range potentially greater than 93dB, a signal to noise ratio #SNR# of up to 61dB, and dissipation of less than 1mW with a 5V power supply. 1 Boyd Fowler, Abbas El Gamal, and David X. D. Yang 2 Charge-coupled devices #CCD# are at present the most widely used technology for implementing area image sensors. CCD image sensors have their shortcomings, however. They su#er from low yields, they consume too muchpower #3#, and they are plagued with SNR limitations due to the shifting and detection of analog charge packets, and the fact that data is communicated o# chip in analog form. Several alternatives to CCD area image sensors that use st...

Automatic Synthesis of CMOS Digital/Analog Converters by Robert McKinstry Robinson Neff Doctor of Philosophy in Engineering -- Electrical Engineering and Computer Sciences University of California at Berkeley Professor Paul R. Gray, Chair Synthesis of analog functional blocks in integrated circuits offers promise for improved designer productivity. By developing module generators for commonly used analog circuit elements, a synthesis methodology may be matched to a particular application, with approaches and algorithms determined by the particular needs of target circuit type. An analog circuit designer should be able to input design specifications and underlying technology information, and a synthesis methodology should determine circuit parameter values and dimensions, creating the required mask layouts. Slow, tedious design and redesign methods should be replaced by one in which the computer finds minimum cost designs which meet performance requirements. This work implements synthesis methods for a widely used analog block, the digital/analog converter (DAC).

The goal of this research was to design a low power 8-bit, 200 MHz digital-to-analog converter suitable for use in an integrated basestation transmitter – and eventually in a transceiver. There were many challenges throughout the design process, including determining the matching requirements of the devices, investigating what percentage of segmentation should be used, and examining the signal-to-noise ratio vs. power tradeoff. A filter and mixer that directly follow the digital-to-analog converter were fully designed. A prototype of the DAC, filter, and mixer that represented the RF front-end of a basestation transmitter on the same silicon was built in a.25 μm process. To test the chip, a 4-layer PCB board was also designed. Acknowledgment Graduate school here at Berkeley has been a fantastic experience. I have never experienced an environment that has so much intensity – not just academically but socially as well. The university provides the opportunity for a balanced life, a benefit that cannot be underestimated. I’d like to thank a few people who have enriched my years here.

The implementation of active pixel based image sensors in CMOS technology is becoming increasingly important forproducing imaging systems that can be manufactured with low cost, low power, simple interface, and with good image quality. The major obstacle in the design of CMOS imagers is Fixed Pattern Noise (FPN) and Signal-to-Noise-Ratio (SNR) of the video output. This research focuses on minimizing FPN and improving SNR in linear CMOS image sensors which are needed in scanning and swiping applications such as nger print sensing, spectroscopy, and medical imaging systems. FPN is reduced in this research through the use of closed loop operational ampli ers in active pixels and through performing Correlated Double Sampling (CDS). SNR is improved by increasing the pixel saturation voltage. This thesis concludes that FPN can be reduced using the closed loop opamp bu ers. The major FPN noise sources are the shot noise from the photodiode, kTC noise from the sampling capacitors, and o set mismatches in the sample and hold ampli ers all of which are not compensated by CDS. Sample and hold ampli er o set mismatch is identi ed as

Two main reasons for variation of current output of current source are temperature dependency and process dependency of output current. Therefore in current references we try to compensate these two major factors. This paper reviews some important current reference in bipolar and CMOS technolgy I.

The design of analog and radio-frequency (RF) circuits in CMOS technology becomes increasingly more difficult as device modeling faces new challenges in deep submicrometer processes and emerging circuit applications. The sophisticated set of characteristics used to represent today's "digital" technologies often proves inadequate for analog and RF design, mandating many additional measurements and iterations to arrive at an acceptable solution. This paper describes a set of characterization vehicles that can be employed to quantify the analog behavior of active and passive devices in CMOS processes, in particular, properties that are not modeled accurately by SPICE parameters. Test structures and circuits are introduced for measuring speed, noise, linearity, loss, matching, and dc characteristics. Index Terms--- Analog circuits, device noise, mismatch, MOS devices, RF circuits, technology characterization. I. INTRODUCTION A S CMOS technology continues to benefit from both scaling an...