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The synchronous languages twelve years later
 Proceedings of the IEEE
, 2003
"... Abstract — Twelve years ago, Proceedings of the IEEE devoted a special section to the synchronous languages. This article discusses the improvements, difficulties, and successes that have occured with the synchronous languages since then. Today, synchronous languages have been established as a techn ..."
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Cited by 92 (6 self)
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Abstract — Twelve years ago, Proceedings of the IEEE devoted a special section to the synchronous languages. This article discusses the improvements, difficulties, and successes that have occured with the synchronous languages since then. Today, synchronous languages have been established as a technology of choice for modeling, specifying, validating, and implementing realtime embedded applications. The paradigm of synchrony has emerged as an engineerfriendly design method based on mathematicallysound tools.
Preemption in Concurrent Systems
, 1993
"... Process preemption deals with controlling the life and death of concurrent processes. Welldefined preemption mechanisms are essential in controldominated reactive and realtime programming, and accurate handling of preemption requires a timedependent model. We first informally discuss what pre ..."
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Cited by 64 (0 self)
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Process preemption deals with controlling the life and death of concurrent processes. Welldefined preemption mechanisms are essential in controldominated reactive and realtime programming, and accurate handling of preemption requires a timedependent model. We first informally discuss what preemption is about and argue for the need of preemption primitives that are fully orthogonal with sequencing and concurrency ones. Then, we formally present the preemption operators of the Esterel zerodelay process calculus, which is a theoretical version of the Esterel synchronous programming language. 1 Introduction In concurrent systems, one deals with concurrent processes that coordinate with each other. Coordination can result from information exchange, using for example messages circulating on channels with possibly some implied synchronization. It can also result from process preemption, which is a more implicit control mechanism that consists in denying the right to work to a pro...
Constructive Analysis of Cyclic Circuits
, 1996
"... Traditionally, circuits with combinational loops are found only in asynchronous designs. However, combinational loops can also be useful for synchronous circuit design. Combinational loops can arise from highlevel language behavioral compiling, and can be used to reduce circuit size. We provide a s ..."
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Cited by 63 (2 self)
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Traditionally, circuits with combinational loops are found only in asynchronous designs. However, combinational loops can also be useful for synchronous circuit design. Combinational loops can arise from highlevel language behavioral compiling, and can be used to reduce circuit size. We provide a symbolic algorithm that detects if a sequential circuit with combinational loops exhibits standard synchronous behavior, and if so, produces an equivalent circuit without combinational loops. We present applications to hardware and software synthesis from the Esterel synchronous programming language.
The Specification and Execution of Heterogeneous Synchronous Reactive Systems
 University of California, Berkeley
, 1995
"... Electronic systems are becoming more complex. Using subproblemspecific languages simplifies their design, but presents the problem of connecting the parts. I propose a system description scheme for reactive systems (systems that maintain a dialog with their environment) that supports such heterogen ..."
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Cited by 50 (0 self)
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Electronic systems are becoming more complex. Using subproblemspecific languages simplifies their design, but presents the problem of connecting the parts. I propose a system description scheme for reactive systems (systems that maintain a dialog with their environment) that supports such heterogeneity. I expect to contribute the system description scheme, a mathematical framework for it, a set of efficient algorithms for simulating these systems, and a practical implementation of the scheme. My prototype compiler suggests this scheme can be made practical, and the mathematical framework is nearly complete. I expect this work to make designing complex, heterogeneous reactive systems fast and simple. 1 Introduction Electronic systems are growing more complex. Describing these with a diverse set of languages, each suited to a particular subtask, can greatly simplify designing these systems, but the problem of connecting the subtasks arises. For example, a convenient descriptionof the d...
The semantics and execution of a synchronous blockdiagram language
 Science of Computer Programming
"... We present a new block diagram language for describing synchronous software. It coordinates the execution of synchronous, concurrent software modules, allowing realtime systems to be assembled from precompiled blocks specified in other languages. The semantics we present, based on fixed points, is ..."
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Cited by 34 (17 self)
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We present a new block diagram language for describing synchronous software. It coordinates the execution of synchronous, concurrent software modules, allowing realtime systems to be assembled from precompiled blocks specified in other languages. The semantics we present, based on fixed points, is deterministic even in the presence of instantaneous feedback. The execution policy develops a static schedule—a fixed order in which to execute the blocks that makes the system execution predictable. We present exact and heuristic algorithms for finding schedules that minimize system execution time, and show that good schedules can be found quickly. The scheduling algorithms are applicable to other problems where large systems of equations need to be solved.
Sequential Synthesis Using S1S
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2000
"... We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematically elegant solutions to problems arising in the synthesis and optimization of synchronous digital hardware. Specifically, we derive ..."
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Cited by 12 (4 self)
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We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematically elegant solutions to problems arising in the synthesis and optimization of synchronous digital hardware. Specifically, we derive a logical expression which yields a single finite state automaton characterizing the set of implementations that can replace a component of a larger design. The power of our approach is demonstrated by the fact that it generalizes immediately to arbitrary interconnection topologies, and to designs containing nondeterminism and fairness. We also describe control aspects of sequential synthesis and relate controller realizability to classical work on program synthesis and tree automata.
Modular code generation from synchronous block diagrams — modularity vs. code size
 in Proc. POPL
, 2009
"... We study modular, automatic code generation from hierarchical block diagrams with synchronous semantics. Such diagrams are the fundamental model behind widespread tools in the embedded software domain, such as Simulink and SCADE. Code is modular in the sense that it is generated for a given composit ..."
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Cited by 12 (5 self)
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We study modular, automatic code generation from hierarchical block diagrams with synchronous semantics. Such diagrams are the fundamental model behind widespread tools in the embedded software domain, such as Simulink and SCADE. Code is modular in the sense that it is generated for a given composite block independently from context (i.e., without knowing in which diagrams the block is to be used) and using minimal information about the internals of the block. In previous work, we have shown how modular code can be generated by computing a set of interface functions for each block and a set of dependencies between these functions that is exported along with the interface. We have also introduced a quantified notion of modularity in terms of the number of interface functions generated per block, and showed how to minimize this number, which is essential for scalability. Finally, we have exposed
Ternary Simulation: A Refinement of Binary Functions or an Abstraction of RealTime Behaviour?
 PROCEEDINGS OF THE 3RD WORKSHOP ON DESIGNING CORRECT CIRCUITS (DCC96
, 1996
"... We prove the equivalence between the ternary circuit model and a notion of intuitionistic stabilization bounds. The results are obtained as an application of the timing interpretation of intuitionistic propositional logic presented in [12]. We show that if one takes an intensional view of the ternar ..."
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Cited by 9 (3 self)
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We prove the equivalence between the ternary circuit model and a notion of intuitionistic stabilization bounds. The results are obtained as an application of the timing interpretation of intuitionistic propositional logic presented in [12]. We show that if one takes an intensional view of the ternary model then the delays that have been abstracted away can be completely recovered. Our intensional soundness and completeness theorems imply that the extracted delays are both correct and exact; thus we have developed a framework which unifies ternary simulation and functional timing analysis. Our focus is on the combinational behaviour of gatelevel circuits with feedback.
Efficient Analysis of Cyclic Definitions
, 1999
"... We present a new algorithm for detecting semantic combinational cycles that is simpler and more efficient than earlier algorithms found in the literature. Combinational circuits with syntactic cycles often arise in processor and busbased designs. The intention is that external inputs and delay ..."
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Cited by 8 (0 self)
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We present a new algorithm for detecting semantic combinational cycles that is simpler and more efficient than earlier algorithms found in the literature. Combinational circuits with syntactic cycles often arise in processor and busbased designs. The intention is that external inputs and delay elements such as latches break these cycles, so that no "semantic" cycles remain. Unbroken semantic cycles are considered a design error in this context. Such unbroken cycles may also occur inadvertently in compositions of Mealy machines.
The Synthesis of Cyclic Combinational Circuits
 In Design Automation Conference (DAC
, 2003
"... Digital circuits are called combinational if they are memoryless: they have outputs that depend only on the current values of the inputs. Combinational circuits are generally thought of as acyclic (i.e., feedforward) structures. And yet, cyclic circuits can be combinational. Cycles sometimes occur ..."
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Cited by 8 (1 self)
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Digital circuits are called combinational if they are memoryless: they have outputs that depend only on the current values of the inputs. Combinational circuits are generally thought of as acyclic (i.e., feedforward) structures. And yet, cyclic circuits can be combinational. Cycles sometimes occur in designs synthesized from highlevel descriptions. Feedback in such cases is carefully contrived, typically occurring when functional units are connected in a cyclic topology. Although the premise of cycles in combinational circuits has been accepted, and analysis techniques have been proposed, no one has attempted the synthesis of circuits with feedback at the logic level.