Results 1  10
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29
A fully implicit algorithm for exact state minimization
, 1993
"... State minimization of incompletely specified machines is an important step of FSM synthesis. An exact algorithm consists of generation of prime compatibles and solution of a binate covering problem. This paper presents an implicit algorithm for exact state minimization of FSM’s. We describe how to d ..."
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Cited by 31 (9 self)
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State minimization of incompletely specified machines is an important step of FSM synthesis. An exact algorithm consists of generation of prime compatibles and solution of a binate covering problem. This paper presents an implicit algorithm for exact state minimization of FSM’s. We describe how to do implicit prime computation and implicit binate covering. We show that we can handle sets of compatibles and prime compatibles of cardinality up to 2 1500. We present the first published algorithm for fully implicit exact binate covering. We show that we can reduce and solve binate tables with up to 10 6 rows and columns. The entire branchandbound procedure is carried on implicitly. We indicate also where such examples arise in practice. 1
Robust Techniques For Watermarking Sequential Circuit Designs
 36th ACM/IEEE Design Automation Conference Proceedings
, 1999
"... We present a methodology for the watermarking of synchronous sequential circuits that makes it possible to identify the authorship of designs by imposing a digital watermark on the state transition graph of the circuit. The methodology is applicable to sequential designs that are made available as f ..."
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Cited by 21 (0 self)
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We present a methodology for the watermarking of synchronous sequential circuits that makes it possible to identify the authorship of designs by imposing a digital watermark on the state transition graph of the circuit. The methodology is applicable to sequential designs that are made available as firm Intellectual Property (IP), the designation commonly used to characterize designs specified as structural descriptions or circuit netlists.
Covering Conditions and Algorithms for the Synthesis of SpeedIndependent Circuits
 IEEE Transactions on ComputerAided Design
, 1998
"... This paper presents theory and algorithms for the synthesis of standard Cimplementations of speedindependent circuits. These implementations are blocklevel circuits which may consist of atomic gates to perform complex functions in order to ensure hazardfreedom. First, we present boolean covering ..."
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Cited by 13 (4 self)
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This paper presents theory and algorithms for the synthesis of standard Cimplementations of speedindependent circuits. These implementations are blocklevel circuits which may consist of atomic gates to perform complex functions in order to ensure hazardfreedom. First, we present boolean covering conditions that guarantee the standard Cimplementations operate correctly. Then, we present two algorithms that produce optimal solutions to the covering problem. The first algorithm is always applicable but does not complete on large circuits. The second algorithm, motivated by our observation that our covering problem can often be solved with a single cube, finds the optimal singlecube solution when such a solution exists. When applicable, the second algorithm is dramatically more efficient than the first, more general algorithm. We present results for benchmark specifications which indicate that our singlecube algorithm is applicable on most benchmark circuits and reduces runtimes by ...
Sequential Synthesis Using S1S
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2000
"... We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematically elegant solutions to problems arising in the synthesis and optimization of synchronous digital hardware. Specifically, we derive ..."
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Cited by 12 (4 self)
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We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematically elegant solutions to problems arising in the synthesis and optimization of synchronous digital hardware. Specifically, we derive a logical expression which yields a single finite state automaton characterizing the set of implementations that can replace a component of a larger design. The power of our approach is demonstrated by the fact that it generalizes immediately to arbitrary interconnection topologies, and to designs containing nondeterminism and fairness. We also describe control aspects of sequential synthesis and relate controller realizability to classical work on program synthesis and tree automata.
Dynamic Scheduling and Synchronization Synthesis of Concurrent Digital Systems under SystemLevel Constraints
, 1994
"... We present in this paper a novel control synthesis technique for systemlevel specifications that are better described as a set of concurrent synchronous descriptions, their synchronizations and constraints'. The proposed synthesis ' technique considers' the degrees of freedom introduced by the conc ..."
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Cited by 8 (0 self)
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We present in this paper a novel control synthesis technique for systemlevel specifications that are better described as a set of concurrent synchronous descriptions, their synchronizations and constraints'. The proposed synthesis ' technique considers' the degrees of freedom introduced by the concurrent models' and by the environment in order to satisfy the design constraints'.
A New Algorithm For The Reduction Of Incompletely Specified Finite State Machines
 In ICCAD, 482–489
, 1998
"... We propose a new algorithm to the problem of state reduction in incompletely specified finite state machines. This algorithm is not based on the enumeration of compatible sets, and, therefore, its performance is not dependent on the number of prime compatibles. We prove that the algorithm is exact a ..."
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Cited by 8 (0 self)
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We propose a new algorithm to the problem of state reduction in incompletely specified finite state machines. This algorithm is not based on the enumeration of compatible sets, and, therefore, its performance is not dependent on the number of prime compatibles. We prove that the algorithm is exact and present results that show that, in a set of hard problems, it is much more efficient than both the explicit and implicit approaches based on the enumeration of compatible sets. 1 Introduction The reduction of finite state machines is a well known problem of great importance in sequential circuit synthesis. For completely specified finite state machines (FSM), the state reduction problem can be solved in polynomial time [13]. For incompletely specified finite state machines (ISFSM), the problem is known to be NPcomplete [15]. Nonetheless, exact and heuristic algorithms are commonly used in practice, and it is possible, in many cases of practical importance, to obtain exact solutions. The...
Limits of Exact Algorithms For Inference of Minimum Size Finite State Machines
 In Proceedings of the Seventh Workshop on Algorithmic Learning Theory, number 1160 in Lecture Notes in Artificial Intelligence
, 1996
"... . We address the problem of selecting the minimum sized finite state machine consistent with given input/output samples. The problem can be solved by computing the minimum finite state machine equivalent to a finite state machine without loops obtained from the training set. We compare the performan ..."
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Cited by 6 (2 self)
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. We address the problem of selecting the minimum sized finite state machine consistent with given input/output samples. The problem can be solved by computing the minimum finite state machine equivalent to a finite state machine without loops obtained from the training set. We compare the performance of four algorithms for this task: two algorithms for incompletely specified finite state machine reduction, an algorithm based on a well known explicit search procedure and an algorithm based on a new implicit search procedure that is introduced in this paper. 1 Introduction and Related Work We address the problem of inferring the finite state machine (FSM) with minimum number of states that is consistent with a given training set. This problem is important for the machine learning community because of the well known connections between hypothesis compactness and predictive accuracy. This problem is equivalent to the problem of determining if there exists a kstate DFA consistent with a ...
Immediate Observability of Discrete Event Systems with Application to UserInterface Design
"... A human interacting with a hybrid system is often presented, through information displays, with a simplified representation of the underlying system. This interface should not overwhelm the human with unnecessary information, and thus usually contains only a subset of information about the true sys ..."
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Cited by 6 (0 self)
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A human interacting with a hybrid system is often presented, through information displays, with a simplified representation of the underlying system. This interface should not overwhelm the human with unnecessary information, and thus usually contains only a subset of information about the true system model, yet, if properly designed, represents an abstraction of the true system which the human is able to use to safely interact with the system [1]. For cases in which the human interacts with all or part of the system from a remote location, and communication has a high cost, the need for a simple abstraction which reduces the amount of information that must be transmitted is of the utmost importance. The user should be able to immediately determine the actual state of the system, based on the information displayed through the interface. In this paper, we derive conditions for immediate observability in which the current state of the system can be unambiguously reconstructed from the output associated with the current state and the last or next event. Then, we show how to construct a discrete event system output function which makes a system immediately observable, and apply this to a reduced state machine which represents an interface.
Permissible Observability Relations in FSM Networks
, 1994
"... Previous attempts to capture the phenomenon of output don’t care sequences for a component in an FSM network have been incomplete. We demonstrate that output don’t care sequencesfor a component can be expressed using a set of observability relations given that its state transition function is kept u ..."
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Cited by 5 (1 self)
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Previous attempts to capture the phenomenon of output don’t care sequences for a component in an FSM network have been incomplete. We demonstrate that output don’t care sequencesfor a component can be expressed using a set of observability relations given that its state transition function is kept unchanged. Each observability relation is permissible in the sense that any implementation compatible with one of them is feasible. The representation for a set of permissible observability relations is not unique. We provide a method to find a set with the minimum number of permissible relations. We briefly discuss the exploitation of permissible observability relations in state minimization, circuit implementation and signal encoding. We have implemented these methods and present some preliminary results on a few small artificially constructed examples. 1