The Steiner tree problem in weighted graphs seeks a minimum weight connected subgraph containing a given subset of the vertices (terminals). We present a new polynomial-time heuristic with an approximation ratio approaching 1 + 2 1:55, which improves upon the previously best-known approximation algorithm of [10] with performance ratio 1:59.

The primal-dual method is a standard tool in the design of algorithms for combinatorial optimization problems. This chapter shows how the primal-dual method can be modified to provide good approximation algorithms for a wide variety of NP-hard problems. We concentrate on results from recent research applying the primal-dual method to problems in network design.

Abstract. The classical Steiner tree problem in weighted graphs seeks a minimum weight connected subgraph containing a given subset of the vertices (terminals). We present a new polynomial-ln 3 time heuristic that achieves a best-known approximation ratio of 1 + ≈ 1.55 for general graphs 2 and best-known approximation ratios of ≈ 1.28 for both quasi-bipartite graphs (i.e., where no two nonterminals are adjacent) and complete graphs with edge weights 1 and 2. Our method is considerably simpler and easier to implement than previous approaches. We also prove the first known nontrivial performance bound (1.5 · OPT) for the iterated 1-Steiner heuristic of Kahng and Robins in quasi-bipartite graphs.

The Steiner minimum tree problem, which asks for a minimum-length interconnection of a given set of termi-nals in the plane, is one of the fundamental problems in Very Large Scale Integration (VLSI) physical design. Although advances in VLSI manufacturing technologies have introduced additional routing objectives, mini-mum length continues to be the primary objective when routing non-critical nets, since the minimum-length

Abstract — This paper presents a very efficient algorithm for performance-driven topology design for interconnects. Given a net, it first generates A-tree1 topology using table lookup and net-breaking. Then a performance-driven post-processing heuristic not restricting to A-tree topology improves the obtained topology by considering the sink positions, required time and load capacitance to achieve better timing. Experimental results show that our new technique can produce topologies with better timing and is hundreds of times faster than traditional approach. I.