This paper describes GBURG, which generates tiny, fast code generators based on finite-state machine pattern matching. The code generators translate postfix intermediate code into machine instructions in one pass (except, of course, for backpatching ad-dresses). A stack-based virtual machine-known as the Lean Virtual Machine (LVM)-tuned for fast code generation is also described. GBURG translates the two-page LVM-to-x86 specification into a code generator that fits entirely in an 8 KB I-cache and that emits x86 code at 3.6 MB/set on a 266-MHz P6. Our just-in-time code generator translates and executes small benchmarks at speeds within a factor of two of executables derived from the conventional compile-time code generator on which it is based.

this paper focuses on the peephole optimizer in the Amsterdam Compiler Kit (ACK) [6].

Assignment ImplicitAssignment Assignment PhiAssignment Jump CondJump Return The subclasses play the following roles: EmptyRegisterTransfer: used in the instruction builder to represent transfers that only set flags. See Chapter 8. RegisterTransferSet: represents sets of RegisterTransfers to be performed concurrently. Theoretically, this is a recursive structure, since it could contain an instance of itself; however, this is never allowed. Its only instance variable is transfers, an OrderedCollection of the component transfers. Call: represents procedure calls. Its instance variables are method, the Register containing the callee's address; returnValueRegister, the Register in which the result of the call will be found; and argumentLogicalRegisters, an OrderedCollection of the Registers that contain the receiver and the first two arguments. AbstractAssignment: the abstract superclass of all classes representing assignments to some storage. Its only instance variable is destinatio...

. In this paper we describe a formal verification of transformations for peephole optimization using the PVS system [12]. Our basic approach is to develop a generic scheme to mechanize these kinds of verifications for a large class of machine architectures. This generic scheme is instantiated with a formalization of a non-trivial stack machine [14] and a PDP-11 like two-address machine [2], and we prove the correctness of more than 100 published peephole optimization rules for these machines. In the course of verifying these transformations we found several errors in published peephole transformation steps [14]. From the information of failed proof attempts, however, we were able to discover strengthened preconditions for correcting the erroneous transformations. Keywords: formal verification, transformations, higher-order logic, reusability of specifications. 1 Introduction Peephole optimization is generally understood as the replacement of a sequence of instructions by ...

In an era of rapid design of microprocessors for desktop systems, embedded systems, and handheld computing devices, the timely construction of systems software is essential. Systems software, such as assemblers, compilers, and debuggers, must be constructed before development of application software for a microprocessor can commence. However, the implementation of such machine-specific applications is difficult and time consuming. Therefore, to remain competitive, it is imperative that systems software designs focus on portability to reduce implementation time and ensure rapid delivery of complete systems to the market. This dissertation presents the Computing System Description Language (CSDL) framework that addresses these rapid development requirements. We illustrate the CSDL framework by developing an instruction-set description component (RTL), an optional procedure calling convention description component (CCL), and the mechanism we use to extend extant descriptions (CSDL). RTL and its accompanying microinstruction descriptions (RTL) further the state-of-the-art in specifying semantics of machine instructions. RTL adds a new type system and abstract syntax that facilitates more accurate specification and automatic detection of errors by RTL manipulators. RTL machine descriptions are also application independent---they completely separate the specification of semantics from the application's implementation. The CCL specification language is the first work to formally describe procedure calling conventions. We demonstrate two distinct uses for CCL descriptions: code generation and fault detection. Using CCL we have built compilers that are more robust, and found and diagnosed faults in production compilers. CCL, RTL, and RTL descriptions are bound together u...

We present a retargetable, machine-level framework that tightly integrates the three primary functions performed by an optimizer: code generation, register allocation and code improvements. This framework is highly retargetable, able to fully exploit unique architectural features and, unlike most integrated frameworks, easily extended to include a comprehensive set of local and global optimizations. A unique approach to performing transformations improves register allocation, reduces interactions between the code improvement phases and enhances retargetability by eliminating the need to determine an effective phase ordering for each target architecture. 1 Introduction Many retargetable optimizing compilers perform code improvements on fixed, high-level intermediate representations [TSK+83] [CH84]. While these representations promote retargetability by allowing much of the optimizer to be machine-independent, they make it difficult to exploit the unique architectural features of each ...

The proliferation of high-performance microprocessors in recent years has made the development of systems software, such as compilers, assemblers, linkers, debuggers, simulators, and other related tools, more challenging than ever. When a new processor is introduced, each of these applications must be rewritten or retargeted to the new machine. This paper describes a description system, called CSDL, that permits the specification---in a concise, easily understood notation---of all aspects of a computing system that must be known in order to automate the construction of high-quality systems software. Unlike past machine description languages, and as the term computing system indicates, this new description system spans the boundary between hardware and software. CSDL descriptions are modular and extensible, providing a flexible system for specifying computing system information that can be shared among many different applications. 1 Introduction The proliferation of high-performance mi...

The log files generated while operating a file system in disconnected mode grow to substantial sizes. Eliminating redundant or useless operations in these logs can free up scarce disk space on laptops, reduce replay times, and reduce the frequency of data conflict. Our approach uses a rule-based portable peephole optimizer for compilers. This suggests a general method of optimization for any system that performs logging at the vnode layer. 1. Introduction One goal of mobile computing is to provide users with a system that faithfully emulates the desktop environment. The mobile environment makes this goal a difficult one to reach because of limitations such as sporadic, low-bandwidth networks. Moreover, mobile computers tend to be resource poor, so that consumption of resources, such as disk space, demands careful control. The conventional paradigm for modern computing systems is distributed computing. An essential service in a distributed computing environment is the (distributed) fil...

Vikram Rao. IA-64 code generation. #Under the direction of Dr. Tom Conte#. This work presents an approach to code generation for a new 64-bit Explicitly Parallel Instruction Computing #EPIC# architecture from Intel, called IA-64. The major contribution of this work is the design of a machine independent optimizer, munger, that transforms code generated originally for a Very Long Instruction Word #VLIW# processor, called Tinker, to one that can run on the IA-64 architecture. The munger does this transformation by reading in a set of rules that specify a mapping from Tinker speci#c code to IA-64 speci#c code. The aim is to do this transformation outside the compiler back-end, thereby being able to take advantage of any optimizations that the back-end might perform on the code. This would also preclude rewriting the existing back-end signi#cantly, to support the new architecture. The primary motivation for this approach was the fairly large similarity between the Tinker, and the IA-64 ar...

Vikram Rao. IA-64 code generation. #Under the direction Dr. Tom Conte#. This work presents approach code generation new 64-bit Explicitly Parallel Instruction Computing #EPIC# architecture from Intel, called IA-64. The major contribution this work the design a machine independent optimizer, munger, that transforms code generated originally for a Very Long Instruction Word #VLIW# processor, called Tinker, one that can run IA-64 architecture. The munger does this transformation reading rules that specify mapping from Tinker speci#c code IA-64 speci#c code. The do this transformation outside the compiler back-end, thereby being able take advantage optimizations that back-end might perform code. This would also preclude rewriting the existing back-end signi#cantly, support the new architecture. The primary motivation this approach was the fairly large similarity between the Tinker, and the IA-64 architectures. Besides, Tinker is experimental VLIW architecture that supports a number featur...