This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inverter Graphs (AIGs), the networks of two-input ANDs and inverters. The optimization works by alternating DAG-aware AIG rewriting, which reduces area by sharing common logic without increasing delay, and algebraic AIG balancing, which minimizes delay without increasing area. The new technology-independent flow is implemented in a public-domain tool ABC. Experiments on large industrial benchmarks show that the proposed methodology scales to very large designs and is several orders of magnitude faster than SIS and MVSIS while offering comparable or better quality when measured by the quality of the network after mapping. 1

The paper explores several ways to improve the speed and capacity of combinational equivalence checking based on Boolean satisfiability (SAT). State-of-the-art methods use simulation and BDD/SAT sweeping on the input side (i.e. proving equivalence of some internal nodes in a topological order), interleaved with attempts to run SAT on the output (i.e. proving equivalence of the output to constant 0). This paper improves on this method by (a) using more intelligent simulation, (b) using CNF-based SAT with circuit-based decision heuristics, and (c) interleaving SAT with low-effort logic synthesis. Experimental results on public and industrial benchmarks demonstrate substantial reductions in runtime, compared to the current methods. In several cases, the new solver succeeded in solving previously unsolved problems. 1

This paper describes an improved approach to Boolean network optimization using internal don’t-cares. The improvements concern the type of don’t-cares computed, their scope, and the computation method. Instead of the traditional compatible observability don’t-cares (CODCs), we introduce and justify the use of complete don’t-cares (CDC). To ensure the robustness of the don’t-care computation for very large industrial networks, a windowing scheme is implemented, which computes substantial subsets of the CDCs in reasonable time. Finally, we give a SAT-based don’t-care computation algorithm, which is more efficient than BDD-based algorithms. Experimental results confirm that these improvements work well in practice. Complete don’t-cares allow for a reduction in the number of literals compared to the CODCs. Windowing guarantees robustness, even for very large benchmarks, to which previous methods cannot be applied. SAT reduces the runtime, making don’t-cares affordable for a variety of other Boolean methods applied to the network. 1

A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are checked independently. By checking parity on the present state instead of the next state, this technique allows detection of errors in bistable elements (that were hitherto not detected by many previous techniques) while requiring no changes in the original machine specifications. This paper also examines design choices with respect to parity prediction circuits. Two such examined choices are the multi-parity-group and the single-paritygroup techniques. A new state encoding technique based on the JEDI program is developed for the synthesis of the next-state logic with an additional parity output. Synthesis results produced by our proposed procedure for the MCNC'89 FSM benchmark circuits show on average a 25% reduction in literal counts compared to previous techniques. 1.

Abstract Lava is a system for designing, specifying, verifying and implementing hardware. It is embedded in the functional programming language Haskell, which means that hardware descriptions are first-class objects in Haskell. We are thus able to use modern programming language features, such as higher-order functions, polymorphism, type classes and laziness, in hardware descriptions. We present two rather different versions of Lava. One version realises the embedding by using monads to keep track of the information specified in a hardware description. The other version uses a new language construct, called observable sharing, which eliminates the need for monads so that descriptions are much cleaner. Adding observable sharing to Haskell is a non-conservative extension, meaning that some properties of Haskell are lost. We thus investigate to what extent we are still allowed to use a normal Haskell compiler or interpreter. We also introduce an embedded language for specifying properties. The use of this language is two-fold. On the one hand, we can use it to specify and later formally verify properties of the described circuits. On the other hand, we can use it to specify and randomly test properties of normal Haskell programs. As a bonus, since hardware descriptions are embedded in Haskell, we can also use it to test our circuit descriptions.

This paper describes an efficient implementation of sequential synthesis that uses induction to detect and merge sequentiallyequivalent nodes. State-encoding, scan chains, and test vectors are essentially preserved. Moreover, the sequential synthesis results are sequentially verifiable using an independent inductive prover similar to that used for synthesis, with guaranteed completeness. Experiments with this sequential synthesis show effectiveness. When applied to a set of 20 industrial benchmarks ranging up to 26K registers and up to 53K 6-LUTs, average reductions in register and area are 12.9 % and 13.1 % respectively while delay is reduced by 1.4%. When applied to the largest academic benchmarks, an average reduction in both registers and area is more than 30%. The associated sequential verification is also scalable and runs about 2x slower than synthesis. The implementation is available in the synthesis and verification system ABC. 1

Various languages have been proposed to describe synchronous hardware at an abstract, yet synthesisable level. We propose a uniform framework within which such languages can be developed, and combined together for simulation, synthesis, and verification. We do this by embedding the languages in Lava --- a hardware description language (HDL), itself embedded in the functional programming language Haskell. The approach allows us to easily experiment with new formal languages and language features, and also provides easy access to formal verification tools aiding program verification.

We present a performance-driven programmable logic array mapping algorithm (PLAmap) for complex programmable logic device architectures consisting of a large number of PLA-style logic cells. The primary objective of the algorithm is to minimize the depth of the mapped circuit. We also develop several techniques for area reduction, including threshold control of PLA fanouts and product terms, slack-time relaxation, and PLA packing. We compare PLAmap with a previous algorithm TEMPLA (Anderson and Brown 1998) and a commercial tool Altera Multiple Array MatriX (MAX) + PLUS II (Altera Corporation 2000) using Microelectronics Center of North Carolina (MCNC) benchmark circuits. With a relatively small area overhead, PLAmap reduces circuit depth by 50% compared to TEMPLA and reduces circuit delay by 48% compared to MAX + PLUS II v9.6.

One of the crucial problems multi-level logic synthesis techniques for multi-output boolean functions f = (f 1 ; : : : ; fm ) : f0; 1g n ! f0; 1g m have to deal with is finding sublogic which can be shared by different outputs, i.e., finding boolean functions ff = (ff 1 ; : : : ; ff h ) : f0; 1g p ! f0; 1g h which can be used as common sublogic of good realizations of f1 ; : : : ; fm . In this paper we present an efficient robdd based implementation of this Common Decomposition Functions Problem (cdf). Formally, cdf is defined as follows: Given m boolean functions f1 ; : : : ; fm : f0; 1g n ! f0; 1g, and two natural numbers p and h, find h boolean functions ff 1 ; : : : ; ff h : f0; 1g p ! f0; 1g such that 81 k m there is a decomposition of fk of the form fk (x1 ; : : : ; xn ) = g (k) (ff 1 (x1 ; : : : ; xp ); : : : ; ff h (x1 ; : : : ; xp ); ff (k) h+1 (x 1 ; : : : ; xp ); : : : ; ff (k) r k (x 1 ; : : : ; xp ); xp+1 ; : : : ; xn ) using a minimal number rk of...

Both non-determinism and multi-level networks compactly characterize the flexibility allowed in implementing a circuit. A theory for representing and manipulating non-deterministic (ND) networks is developed. The theory supports all the network manipulations commonly applied to deterministic binary networks, such as node minimization, elimination, and decomposition. It is shown that an ND network's behavior can be interpreted in three ways, all of which coincide when the network is deterministic. Operations performed on ND networks are analyzed under each interpretation for their effect on the networks' behaviors. Some operations, if not modified appropriately, can increase different behaviors and thus might cause an ND network to violate its external specification. Several methods are studied to guarantee that this does not occur.