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56
DAGaware AIG rewriting: A fresh look at combinational logic synthesis
 In DAC ’06: Proceedings of the 43rd annual conference on Design automation
, 2006
"... This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using AndInverter Graphs (AIGs), the networks of twoinput ANDs and inverters. The optimization works by alternating DAGaware AIG rew ..."
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Cited by 76 (32 self)
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This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using AndInverter Graphs (AIGs), the networks of twoinput ANDs and inverters. The optimization works by alternating DAGaware AIG rewriting, which reduces area by sharing common logic without increasing delay, and algebraic AIG balancing, which minimizes delay without increasing area. The new technologyindependent flow is implemented in a publicdomain tool ABC. Experiments on large industrial benchmarks show that the proposed methodology scales to very large designs and is several orders of magnitude faster than SIS and MVSIS while offering comparable or better quality when measured by the quality of the network after mapping. 1
Improvements to Combinational Equivalence Checking
 In Proc. Int’l Conf. on ComputerAided Design
, 2006
"... The paper explores several ways to improve the speed and capacity of combinational equivalence checking based on Boolean satisfiability (SAT). Stateoftheart methods use simulation and BDD/SAT sweeping on the input side (i.e. proving equivalence of some internal nodes in a topological order), inte ..."
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Cited by 44 (20 self)
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The paper explores several ways to improve the speed and capacity of combinational equivalence checking based on Boolean satisfiability (SAT). Stateoftheart methods use simulation and BDD/SAT sweeping on the input side (i.e. proving equivalence of some internal nodes in a topological order), interleaved with attempts to run SAT on the output (i.e. proving equivalence of the output to constant 0). This paper improves on this method by (a) using more intelligent simulation, (b) using CNFbased SAT with circuitbased decision heuristics, and (c) interleaving SAT with loweffort logic synthesis. Experimental results on public and industrial benchmarks demonstrate substantial reductions in runtime, compared to the current methods. In several cases, the new solver succeeded in solving previously unsolved problems. 1
SATbased complete don’tcare computation for network optimization
 Proc. DATE '05
"... This paper describes an improved approach to Boolean network optimization using internal don’tcares. The improvements concern the type of don’tcares computed, their scope, and the computation method. Instead of the traditional compatible observability don’tcares (CODCs), we introduce and justify ..."
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Cited by 27 (9 self)
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This paper describes an improved approach to Boolean network optimization using internal don’tcares. The improvements concern the type of don’tcares computed, their scope, and the computation method. Instead of the traditional compatible observability don’tcares (CODCs), we introduce and justify the use of complete don’tcares (CDC). To ensure the robustness of the don’tcare computation for very large industrial networks, a windowing scheme is implemented, which computes substantial subsets of the CDCs in reasonable time. Finally, we give a SATbased don’tcare computation algorithm, which is more efficient than BDDbased algorithms. Experimental results confirm that these improvements work well in practice. Complete don’tcares allow for a reduction in the number of literals compared to the CODCs. Windowing guarantees robustness, even for very large benchmarks, to which previous methods cannot be applied. SAT reduces the runtime, making don’tcares affordable for a variety of other Boolean methods applied to the network. 1
Finite State Machine Synthesis with Concurrent Error Detection
 Proc. International Test Conference
, 1999
"... A new synthesis technique for designing finite state machines with online parity checking is presented. The output logic and the nextstate logic of the finite state machines are checked independently. By checking parity on the present state instead of the next state, this technique allows detectio ..."
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Cited by 25 (6 self)
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A new synthesis technique for designing finite state machines with online parity checking is presented. The output logic and the nextstate logic of the finite state machines are checked independently. By checking parity on the present state instead of the next state, this technique allows detection of errors in bistable elements (that were hitherto not detected by many previous techniques) while requiring no changes in the original machine specifications. This paper also examines design choices with respect to parity prediction circuits. Two such examined choices are the multiparitygroup and the singleparitygroup techniques. A new state encoding technique based on the JEDI program is developed for the synthesis of the nextstate logic with an additional parity output. Synthesis results produced by our proposed procedure for the MCNC'89 FSM benchmark circuits show on average a 25% reduction in literal counts compared to previous techniques. 1.
Embedded Languages for Describing and Verifying Hardware
, 2001
"... Abstract Lava is a system for designing, specifying, verifying and implementing hardware. It is embedded in the functional programming language Haskell, which means that hardware descriptions are firstclass objects in Haskell. We are thus able to use modern programming language features, such as hi ..."
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Cited by 23 (2 self)
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Abstract Lava is a system for designing, specifying, verifying and implementing hardware. It is embedded in the functional programming language Haskell, which means that hardware descriptions are firstclass objects in Haskell. We are thus able to use modern programming language features, such as higherorder functions, polymorphism, type classes and laziness, in hardware descriptions. We present two rather different versions of Lava. One version realises the embedding by using monads to keep track of the information specified in a hardware description. The other version uses a new language construct, called observable sharing, which eliminates the need for monads so that descriptions are much cleaner. Adding observable sharing to Haskell is a nonconservative extension, meaning that some properties of Haskell are lost. We thus investigate to what extent we are still allowed to use a normal Haskell compiler or interpreter. We also introduce an embedded language for specifying properties. The use of this language is twofold. On the one hand, we can use it to specify and later formally verify properties of the described circuits. On the other hand, we can use it to specify and randomly test properties of normal Haskell programs. As a bonus, since hardware descriptions are embedded in Haskell, we can also use it to test our circuit descriptions.
Scalable and scalablyverifiable sequential synthesis
 Proc. ICCAD'08. http://www.eecs.berkeley.edu/~alanmi/publications/2008/iccad08_se q.pdf A. Mishchenko
"... This paper describes an efficient implementation of sequential synthesis that uses induction to detect and merge sequentiallyequivalent nodes. Stateencoding, scan chains, and test vectors are essentially preserved. Moreover, the sequential synthesis results are sequentially verifiable using an inde ..."
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Cited by 18 (14 self)
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This paper describes an efficient implementation of sequential synthesis that uses induction to detect and merge sequentiallyequivalent nodes. Stateencoding, scan chains, and test vectors are essentially preserved. Moreover, the sequential synthesis results are sequentially verifiable using an independent inductive prover similar to that used for synthesis, with guaranteed completeness. Experiments with this sequential synthesis show effectiveness. When applied to a set of 20 industrial benchmarks ranging up to 26K registers and up to 53K 6LUTs, average reductions in register and area are 12.9 % and 13.1 % respectively while delay is reduced by 1.4%. When applied to the largest academic benchmarks, an average reduction in both registers and area is more than 30%. The associated sequential verification is also scalable and runs about 2x slower than synthesis. The implementation is available in the synthesis and verification system ABC. 1
An Embedded Language Framework for Hardware Compilation
 DESIGNING CORRECT CIRCUITS
, 2002
"... Various languages have been proposed to describe synchronous hardware at an abstract, yet synthesisable level. We propose a uniform framework within which such languages can be developed, and combined together for simulation, synthesis, and verification. We do this by embedding the languages in Lava ..."
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Cited by 16 (8 self)
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Various languages have been proposed to describe synchronous hardware at an abstract, yet synthesisable level. We propose a uniform framework within which such languages can be developed, and combined together for simulation, synthesis, and verification. We do this by embedding the languages in Lava  a hardware description language (HDL), itself embedded in the functional programming language Haskell. The approach allows us to easily experiment with new formal languages and language features, and also provides easy access to formal verification tools aiding program verification.
Optimality Study of Logic Synthesis for LUTBased FPGAs
"... Abstract—Fieldprogrammable gatearray (FPGA) logic synthesis and technology mapping have been studied extensively over the past 15 years. However, progress within the last few years has slowed considerably (with some notable exceptions). It seems natural to then question whether the current logics ..."
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Cited by 15 (0 self)
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Abstract—Fieldprogrammable gatearray (FPGA) logic synthesis and technology mapping have been studied extensively over the past 15 years. However, progress within the last few years has slowed considerably (with some notable exceptions). It seems natural to then question whether the current logicsynthesis and technologymapping algorithms for FPGA designs are producing nearoptimal solutions. Although there are many empirical studies that compare different FPGA synthesis/mapping algorithms, little is known about how far these algorithms are from the optimal (recall that both logicoptimization and technologymapping problems are NPhard, if we consider area optimization in addition to delay/depth optimization). In this paper, we present a novel method for constructing arbitrarily large circuits that have known optimal solutions after technology mapping. Using these circuits and their derivatives (called Logic synthesis Examples with Known Optimal (LEKO) and Logic synthesis Examples with Known Upper bounds (LEKU), respectively), we show that although leading FPGA technologymapping algorithms can produce close to optimal solutions, the results from the entire logicsynthesis flow (logic optimization + mapping) are far from optimal. The LEKU circuits were constructed to show where the logic synthesis flow can be improved, while the LEKO circuits specifically deal with the performance of the technology mapping. The best industrial and academic FPGA synthesis flows are around 70 times larger in terms of area on average and, in some cases, as much as 500 times larger on LEKU examples. These results clearly indicate that there is much room for further research and improvement in FPGA synthesis. Index Terms—Circuit optimization, circuit synthesis, design automation, fieldprogrammable gate arrays (FPGAs), optimization methods. I.
PerformanceDriven Mapping for CPLD Architectures
 in Proc. ACM/SIGDA 9th Int. Symp. FieldProgram. Gate Arrays
, 2003
"... We present a performancedriven programmable logic array mapping algorithm (PLAmap) for complex programmable logic device architectures consisting of a large number of PLAstyle logic cells. The primary objective of the algorithm is to minimize the depth of the mapped circuit. We also develop severa ..."
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Cited by 15 (0 self)
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We present a performancedriven programmable logic array mapping algorithm (PLAmap) for complex programmable logic device architectures consisting of a large number of PLAstyle logic cells. The primary objective of the algorithm is to minimize the depth of the mapped circuit. We also develop several techniques for area reduction, including threshold control of PLA fanouts and product terms, slacktime relaxation, and PLA packing. We compare PLAmap with a previous algorithm TEMPLA (Anderson and Brown 1998) and a commercial tool Altera Multiple Array MatriX (MAX) + PLUS II (Altera Corporation 2000) using Microelectronics Center of North Carolina (MCNC) benchmark circuits. With a relatively small area overhead, PLAmap reduces circuit depth by 50% compared to TEMPLA and reduces circuit delay by 48% compared to MAX + PLUS II v9.6.
Communication Based FPGA Synthesis for MultiOutput Boolean Functions
, 1995
"... One of the crucial problems multilevel logic synthesis techniques for multioutput boolean functions f = (f 1 ; : : : ; fm ) : f0; 1g n ! f0; 1g m have to deal with is finding sublogic which can be shared by different outputs, i.e., finding boolean functions ff = (ff 1 ; : : : ; ff h ) : f0; 1 ..."
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Cited by 11 (2 self)
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One of the crucial problems multilevel logic synthesis techniques for multioutput boolean functions f = (f 1 ; : : : ; fm ) : f0; 1g n ! f0; 1g m have to deal with is finding sublogic which can be shared by different outputs, i.e., finding boolean functions ff = (ff 1 ; : : : ; ff h ) : f0; 1g p ! f0; 1g h which can be used as common sublogic of good realizations of f1 ; : : : ; fm . In this paper we present an efficient robdd based implementation of this Common Decomposition Functions Problem (cdf). Formally, cdf is defined as follows: Given m boolean functions f1 ; : : : ; fm : f0; 1g n ! f0; 1g, and two natural numbers p and h, find h boolean functions ff 1 ; : : : ; ff h : f0; 1g p ! f0; 1g such that 81 k m there is a decomposition of fk of the form fk (x1 ; : : : ; xn ) = g (k) (ff 1 (x1 ; : : : ; xp ); : : : ; ff h (x1 ; : : : ; xp ); ff (k) h+1 (x 1 ; : : : ; xp ); : : : ; ff (k) r k (x 1 ; : : : ; xp ); xp+1 ; : : : ; xn ) using a minimal number rk of...