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43
Power minimization in IC design: principles and applications,"
 ACM Transactions on Design Automation of Electronic Systems,
, 1996
"... Abstract Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for des ..."
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Cited by 200 (31 self)
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Abstract Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing design ers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.
HighLevel Power Modeling, Estimation, and Optimization
 IEEE Trans. On Computer Aided Design
, 1998
"... Abstract—Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital verylargescaleintegration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the othe ..."
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Cited by 106 (12 self)
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Abstract—Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital verylargescaleintegration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the other design parameters. This is primarily due to the remarkable success of personal computing devices and wireless communication systems, which demand highspeed computations with low power consumption. In addition, there exists a strong pressure for manufacturers of highend products to keep power under control, due to the increased costs of packaging and cooling this type of devices. Last, the need of ensuring high circuit reliability has turned out to be more stringent. The availability of tools for the automatic design of lowpower VLSI systems has thus become necessary. More specifically, following a natural trend, the interests of the researchers have lately shifted to the investigation of power modeling, estimation, synthesis, and optimization techniques that account for power dissipation during the early stages of the design flow. This paper surveys representative contributions to this area that have appeared in the recent literature. Index Terms — Behavioral and logic synthesis, low power design, power management. I.
A survey of optimization techniques targeting low power circuits
 in Proc. Design Automation Conf
, 1995
"... Abstract—We survey stateoftheart optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered. Keywords—low power, optimization, synthesis I. ..."
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Cited by 77 (0 self)
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Abstract—We survey stateoftheart optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered. Keywords—low power, optimization, synthesis I.
Markovian Analysis of Large Finite State Machines
 IEEE Transactions on CAD
, 1996
"... Regarding finite state machines as Markov chains facilitates the application of probabilistic methods to very large logic synthesis and formal verification problems. In this paper we present symbolic algorithms to compute the steadystate probabilities for very large finite state machines (up to 10 ..."
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Cited by 77 (7 self)
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Regarding finite state machines as Markov chains facilitates the application of probabilistic methods to very large logic synthesis and formal verification problems. In this paper we present symbolic algorithms to compute the steadystate probabilities for very large finite state machines (up to 10 27 states). These algorithms, based on Algebraic Decision Diagrams (ADDs)  an extension of BDDs that allows arbitrary values to be associated with the terminal nodes of the diagrams  determine the steadystate probabilities by regarding finite state machines as homogeneous, discreteparameter Markov chains with finite state spaces, and by solving the corresponding ChapmanKolmogorov equations. We first consider finite state machines with state graphs composed of a single terminal strongly connected component; for this type of systems we have implemented two solution techniques: One is based on the GaussJacobi iteration, the other one is based on simple matrix multiplication. Then we...
LowPower Encodings for Global Communication in CMOS VLSI
, 1997
"... Technology trends and especially portable applications are adding a third dimension (power) to the previously twodimensional (speed, area) VLSI design space [30]. A large portion of power dissipation in high performance CMOS VLSI is due to the inherent difficulties in global communication at high r ..."
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Cited by 52 (2 self)
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Technology trends and especially portable applications are adding a third dimension (power) to the previously twodimensional (speed, area) VLSI design space [30]. A large portion of power dissipation in high performance CMOS VLSI is due to the inherent difficulties in global communication at high rates and we propose several approaches to address the problem. These techniques can be generalized at different levels in the design process. Global communication typically involves driving large capacitive loads which inherently require significant power. However, by carefully choosing the data representation, or encoding, of these signals, the average and peak power dissipation can be minimized. Redundancy can be added in space (number of bus lines), time (number of cycles) and voltage (number of distinct amplitude levels). The proposed codes can be used on a class of terminated offchip boardlevel buses with level signaling, or on tristate onchip buses with level or transition signalin...
G.De Micheli, ”State assignment for low power dissipation
 Custom Integrated Circuits Conference
, 1994
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Compiler Optimization on Instruction Scheduling for Low Power
 IN 13TH INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS. ACM, SEPTERMBER
, 2000
"... In this paper, we investigate the compiler transformation techniques to the problem of scheduling VLIW instructions aimed to reduce the power consumption of VLIW architectures in the instruction bus. The problem can be categorized into two types: horizontal scheduling and vertical scheduling. For th ..."
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Cited by 26 (1 self)
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In this paper, we investigate the compiler transformation techniques to the problem of scheduling VLIW instructions aimed to reduce the power consumption of VLIW architectures in the instruction bus. The problem can be categorized into two types: horizontal scheduling and vertical scheduling. For the case of horizontal scheduling, we propose a bipartitematching scheme for instruction scheduling. We prove that our greedy bipartitematching scheme always gives the optimal switching activities of instruction bus for given VLIW instruction scheduling policies. For the case of vertical scheduling, we prove that the problem is NPhard, and we further propose a heuristic algorithm to solve the problem. Our experiment is performed on Alphabased VLIW architectures and ATOM simulator, and our compiler incorporated by our proposed schemes is implemented based on SUIF and MachSUIF. Experimental results of horizontal scheduling optimization show average 13.30% improvements with 4way issue architecture and average 20.15% improvement with 8way issue architecture for power consumptions of instruction bus as compared with conventional list scheduling for an extensive set of benchmarks. The
Power Optimization of CoreBased Systems by Address Bus Encoding
 IEEE Trans. Very Large Scale Integr. Syst
, 1998
"... This paper presents a solution to the problem of reducing the power dissipated by a digital system containing an intellectual proprietary core processor which repeatedly executes a specialpurpose program. The proposed method relies on a novel, applicationdependent lowpower address bus encoding sc ..."
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Cited by 19 (3 self)
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This paper presents a solution to the problem of reducing the power dissipated by a digital system containing an intellectual proprietary core processor which repeatedly executes a specialpurpose program. The proposed method relies on a novel, applicationdependent lowpower address bus encoding scheme. The analysis of the execution traces of a given program allows an accurate computation of the correlations that may exist between blocks of bits in consecutive patterns; this information can be successfully exploited to determine an encoding which sensibly reduces the bus transition activity. Experimental results, obtained on a set of specialpurpose applications, are very satisfactory; reductions of the bus activity up to 64.8% (41.8% on average) have been achieved over the original address streams. In addition, data concerning the quality and the performance of the automatically synthesized encoding/decoding circuits, as well as the results obtained for a realistic corebased design, indicate the practical usefulness of the proposed power optimization strategy. Index Terms Bus encoding, integrated circuit, intellectual property, low power, power optimization.
Low power realization of finite state machines – a decomposition approach
 ACM Trans. on Deign Automation
, 1996
"... We present in this article a new approach to the synthesis problem for finite state machines with the reduction of power dissipation as a design objective. A finite state machine is decomposed into a number of coupled submachines. Most of the time, only one of the submachines will be activated which ..."
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Cited by 18 (0 self)
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We present in this article a new approach to the synthesis problem for finite state machines with the reduction of power dissipation as a design objective. A finite state machine is decomposed into a number of coupled submachines. Most of the time, only one of the submachines will be activated which, consequently, could lead to substantial savings in power consumption. The key steps in our approach are: (1) decomposition of a finite state machine into submachines so that there is a high probability that state transitions will be confined to the smaller of the submachines most of the time, and (2) synthesis of the coupled submachines to optimize the logic circuits. Experimental results confirmed that our approach produced very good results (in particular, for finite state machines with a large number of states).
TraceDriven SteadyState Probability Estimation in FSMs with Application to Power Estimation
, 1998
"... This paper illustrates, analytically and quantitatively, the effect of highorder temporal correlations on steadystate and transition probabilities in finite state machines (FSMs). As the main theoretical contribution, we extend the previous work done on steadystate probability calculation in FSMs ..."
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Cited by 13 (5 self)
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This paper illustrates, analytically and quantitatively, the effect of highorder temporal correlations on steadystate and transition probabilities in finite state machines (FSMs). As the main theoretical contribution, we extend the previous work done on steadystate probability calculation in FSMs to account for complex spatiotemporal correlations which are present at the primary inputs when the target machine models real hardware and receives data from real applications. More precisely: 1) using the concept of constrained reachability analysis, the correct set of ChapmanKolmogorov equations is constructed; and 2) based on stochastic complementation and iterative aggregation/ disaggregation techniques, exact and approximate methods for finding the state occupancy probabilities in the target machine are presented. From a practical point of view, we show that assuming temporal independence or even using firstorder temporal models is not sufficient due to the inaccuracies induced in steadystate and transition probability calculations. Experimental results show that, if the order of the source is underestimated, not only the set of reachable sets is incorrectly determined, but also the steadystate probability values can be more than 100% off from the correct ones. This strongly impacts the accuracy of the total power estimates that can be obtained via probabilistic approaches.