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On The Implementation of InputFeedforward Delta–Sigma Modulators
"... Abstract—This brief addresses some practical issues on the implementation of the inputfeedforward delta–sigma modulators. First, the timing constraint imposed by the inputfeedforward path is identified and a possible method to relax the constraint is proposed. Second, the drawbacks of the analog a ..."
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Abstract—This brief addresses some practical issues on the implementation of the inputfeedforward delta–sigma modulators. First, the timing constraint imposed by the inputfeedforward path is identified and a possible method to relax the constraint is proposed. Second, the drawbacks of the analog adder needed before the quantizer are explained and a method to eliminate the adder is proposed. Index Terms—Analogtodigital, delta–sigma(16), inputfeedforward, oversampling.
A 0.6V 82dB deltasigma audio ADC using switchedRC integrators
 IEEE Journal of SolidState Circuits
, 2005
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A 12bit 3.125 MHz Bandwidth 0–3 MASH DeltaSigma Modulator
"... Abstract—We demonstrate a 12bit 0–3 MASH deltasigma modulator with a 3.125 MHz bandwidth in a 0.18 m CMOS technology. The modulator has an oversampling ratio of 8 (clock frequency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 dB peak SNR) and consumes 24 mW from a 1.8 V supply. For comparis ..."
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Abstract—We demonstrate a 12bit 0–3 MASH deltasigma modulator with a 3.125 MHz bandwidth in a 0.18 m CMOS technology. The modulator has an oversampling ratio of 8 (clock frequency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 dB peak SNR) and consumes 24 mW from a 1.8 V supply. For comparison purposes, the modulator can be reconfigured as a singleloop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is obtained with 22 mW power consumption. The energy required per conversion step for the 0–3 MASH architecture (0.95 pJ/step) is less than half of that required by the feedback topology (2.57 pJ/step). Index Terms—ADC, analogtodigital conversion, deltasigma modulation, MASH, multibit, multistage, oversampling.
OpAmp Swing Reduction in SigmaDelta Modulators
 Proc. IEEE ISCAS
, 2004
"... An integrator’s output swing reduction technique without deteriorating the SNR of a sigmadelta modulator is proposed. The structure uses input feedforward signals and, for digital feedforward, an additional extra quantizer. The swing of each integrator goes down by 85%. Moreover, the proposed str ..."
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An integrator’s output swing reduction technique without deteriorating the SNR of a sigmadelta modulator is proposed. The structure uses input feedforward signals and, for digital feedforward, an additional extra quantizer. The swing of each integrator goes down by 85%. Moreover, the proposed structure reduces the influence of the harmonic distortion coming from the OpAmp nonlinearity. Detailed analysis and various simulation results verify the operation of the method. 1.
Incremental Data Converters at Low Oversampling Ratios
"... Abstract—In this paper the use of incremental A/D converters with low oversampling ratios is investigated. Incremental A/D converters are able to achieve a higher SQNR than deltasigma modulators at oversampling ratios below 4, allowing them to operate as higher bandwidth converters with medium reso ..."
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Abstract—In this paper the use of incremental A/D converters with low oversampling ratios is investigated. Incremental A/D converters are able to achieve a higher SQNR than deltasigma modulators at oversampling ratios below 4, allowing them to operate as higher bandwidth converters with medium resolution. The impact of removing the input S/H, as well as analyzing their behaviour at an OSR as low as 1 is explored. An eighthorder cascaded incremental A/D converter is analyzed and shown as an example. Index Terms—Deltasigma modulation, incremental analogdigital (A/D) converter, oversampled data conversion, switched capacitor circuits. I.
Architecture alternatives for timeinterleaved and inputfeedforward deltasigma modulators
, 2008
"... This thesis provides architecture alternatives for deltasigma modulators in two areas: highspeed operation based on timeinterleaving and lowvoltage environment by exploiting the inputfeedforward concept. Parallelism based on timeinterleaving can be used to increase the speed of deltasigma mod ..."
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This thesis provides architecture alternatives for deltasigma modulators in two areas: highspeed operation based on timeinterleaving and lowvoltage environment by exploiting the inputfeedforward concept. Parallelism based on timeinterleaving can be used to increase the speed of deltasigma modulators. A novel singlepath timeinterleaved architecture is derived and analyzed. Finite opamp gain and bandwidth result in a mismatch between the noise transfer functions of the internal quantizers which degrades the performance of the new modulator. Two techniques are presented to mitigate the mismatch problem: a hybrid topology where the first stage uses multiple integrators while the rest of the modulator uses a single path of integrators and a digital calibration method. The inputfeedforward technique removes the inputsignal component from the internal nodes of deltasigma modulators. The removal of the signal component reduces the signal swing and distortion requirements for the opamps. These characteristics enable the reliable implementation of deltasigma modulators in modern CMOS technology. Two implementation
Theory and Applications of Incremental 16 Converters
"... c○2004 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other w ..."
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c○2004 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Systematic design of doublesampling 61 A/D converters with a modified noise transfer function
 IEEE Trans. Circuits Syst. II, Exp. Briefs
, 2004
"... (ADCs) are sensitive to path mismatch which causes quantization noise to fold into the signal band. A recent solution for this problem consists of modifying the noise transfer function (NTF) of the modulator such that it has one or several zeros at the Nyquist frequency, next to those in the baseban ..."
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(ADCs) are sensitive to path mismatch which causes quantization noise to fold into the signal band. A recent solution for this problem consists of modifying the noise transfer function (NTF) of the modulator such that it has one or several zeros at the Nyquist frequency, next to those in the baseband. In this brief, we present a systematic design strategy for such ADCs. It consists of finding optimal pole positions for the modified NTF. This can be combined with optimizing the zeros as well. Next, we introduce several efficient structures that have enough degrees of freedom to realize the optimized pole positions. Index Terms—Analog–digital (A/D) conversion, double sampling, sigma–delta 61 modulation. I.
Design of doublesampling 61 modulation A/D converters with bilinear integrators
 IEEE Trans. Circuits Syst. I, Reg. Papers
, 2005
"... Abstract—Doublesampling techniques allow to double the sampling frequency of a switched capacitor 61 analogtodigital convertors without increasing the clock frequency. Unfortunately, path mismatch between the double sampling branches may cause noise folding, which could ruin the modulator’s perfo ..."
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Abstract—Doublesampling techniques allow to double the sampling frequency of a switched capacitor 61 analogtodigital convertors without increasing the clock frequency. Unfortunately, path mismatch between the double sampling branches may cause noise folding, which could ruin the modulator’s performance. The fully floating doublesampling integrator is an interesting building block to be used in such a double sampling 61 modulator because its operation is tolerant to path mismatch. However, this circuit exhibits an undesired bilinear filter effect. This effectively increases the order of the modulator by one. Due to this, previously presented structures don’t have enough freedom to fully control the modulator pole positions. In this paper, we introduce modified topologies for doublesampling 61 modulators built with bilinear integrators. We show that these architectures provide full control of the modulator pole positions and hence can be used to implement any noise transfer function. Additionally, analytical expressions are obtained for the residual folded noise. Index Terms—Analogtodigital convertors, double sampling, 61 modulation. I.
Improved Modeling Of SigmaDelta Modulator NonIdealities
 In Simulink,” in Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, 2005
"... Abstract—The goal of this paper is to present an extension of the behavioral models, implemented in the Matlab/Simulink™ environment, previously presented in [1, 2] and available in [3]. This toolbox allows us to simulate at behavioral level most of the switchedcapacitor (SC) sigmadelta (! " ..."
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Abstract—The goal of this paper is to present an extension of the behavioral models, implemented in the Matlab/Simulink™ environment, previously presented in [1, 2] and available in [3]. This toolbox allows us to simulate at behavioral level most of the switchedcapacitor (SC) sigmadelta (! " ) modulator nonidealities, such as sampling jitter, kT/C noise and operational amplifier limitations (finite bandwidth, finite DC gain, slew rate and saturation). Although very effective in simulating wideband, mediumresolution! " converters the lack of a model for flicker noise and multibit quantizers makes this toolbox less attractive for simulating narrow band high resolution converters. The proposed extension not only fixes this limitation, but introduces a predictive model of the effect of capacitor mismatch in the internal multibit D/A converter. I.