We prove an Ω(n log n) lower bound on the number of nonbusywaiting memory accesses by any deterministic algorithm solving n process mutual exclusion that communicates via shared registers. The cost of the algorithm is measured in the state change cost model, a variation of the cache coherent model. Our bound is tight in this model. We introduce a novel information theoretic proof technique. We first establish a lower bound on the information needed by processes to solve mutual exclusion. Then we relate the amount of information processes can acquire through shared memory accesses to the cost they incur. We believe our proof technique is flexible and intuitive, and may be applied to a variety of other problems and system models.

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This paper introduces solo-valency, a variation on the valency proof technique originated by Fischer, Lynch, and Paterson. The new technique focuses on critical events that influence the responses of solo runs by individual operations, rather than on critical events that influence a protocol’s single decision value. It allows us to derive √ n lower bounds on the time to perform an operation for lock-free implementations of concurrent objects such as linearizable queues, stacks, sets, hash tables, counters, approximate agreement, and more. Time is measured as the number of distinct base objects accessed and the number of stalls caused by contention in accessing memory, incurred by a process as it performs a single operation. We introduce the influence level metric that quantifies the extent to which the response of a solo execution of one process can be changed by other processes. We then prove the existence of a relationship between the space complexity, latency, contention and influence level of all lock-free object implementations. Our results are broad in that they hold for implementations that may use any collection of read-modify-write operations in addition to read and write, and in that they apply even if base objects have unbounded size. 1

Abstract We consider the time complexity of shared-memory mutual exclusion algorithms based on reads, writes, and comparison primitives under the remote-memory-reference (RMR) time measure. For asynchronous systems, a lower bound of \Omega (log N / log log N) RMRs per critical-section entry has been established in previous work, where N is the number of processes. Also, algorithms with O(log N) time complexity are known. Thus, for algorithms in this class, logarithmic or near-logarithmic RMR time complexity is fundamentally required.

We consider asynchronous multiprocessors where processes communicate only by reading or writing shared memory. We show how to implement consensus, all comparison primitives (such as CAS and TAS), and load-linked/store-conditional using only a constant number of remote memory references (RMRs), in both the cache-coherent and the distributedshared-memory models of such multiprocessors. Our implementations are blocking, rather than wait-free: they ensure progress provided all processes that invoke the implemented primitive are live. Our results imply that any algorithm using read and write operations, comparison primitives, and load-linked/storeconditional, can be simulated by an algorithm that uses read and write operations only, with at most a constant blowup in RMR complexity.

60dB 4.20 512 96 ETSI-A ETSI-A ETSI-1 60dB 4.20 1536 512 AWGN-140 AWGN-140 Draft Recommendation G.992.2 140 14 T1.601 #9 1536kbps 256kbps 49 Annex A G.992.2 15 T1.601 #9 1536kbps 256kbps 24 DSL 16 Shortened T1.601#7 1536kbps 256kbps 24 HDSL Table 47. Extended Reach Test Cases NOTE1: A goal of future enhancements of this Recommendation is to make the "Extended Reach Cases" mandatory. NOTE2: Performance levels do not reflect the effect of customer premise wiring, which is expected to reduce data rate.G.992.2G.992.2G.992.2 Draft Recommendation G.992.2 139 ANNEX D D.1 System Performance for North America All test loops specified in this section shall be used for G.992.2 and testing shall confirm to the following: . No power cutback on upstream transmitter. . Margin=4 dB . BER=10 -7 . Background noise = -140 dBm/Hz . Rates, except where noted,

The leader election problem is a fundamental distributed coordination problem. We present leader election algorithms for the cache-coherent (CC) and distributed shared memory (DSM) models using reads and writes only, for which the number of remote memory references (RMRs) is constant in the worst case. The algorithms use splitter-like objects [6, 8] in a novel way for the efficient partitioning of processes into disjoint sets that share work. As there is an \Omega (log n / log log n) lower bound on the RMR complexity of mutual exclusion for n processes using reads and writes only [4], our result separates the mutual exclusion and leader election problems in terms of RMR complexity in both the CC and DSM models. Our result

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We consider the time complexity of adaptive mutual exclusion algorithms, where “time ” is measured by counting the number of remote memory references required per critical-section access. For systems that support (only) read, write, and comparison primitives (such as compare-and-swap), we establish a lower bound that precludes a deterministic algorithm with o(k) time complexity, where k is point contention. In particular, it is impossible to construct a deterministic O(log k) algorithm based on such primitives.