This paper discusses a statistical effect of performance optimization to uncertainty in circuit delay. Performance optimization has an effect of balancing the delay of each path in a circuit, i.e. the delay of long paths are shortened and the delay of short paths are lengthened. In these path-balanced circuits, the uncertainty in circuit delay, which are caused by delay calculation error, manufacturing variability, fluctuation of operating condition, etc., becomes worse by a statistical characteristic of delay. Thus, a highly-optimized circuit may not satisfy delay constraints. In this paper, we demonstrate some examples that uncertainty in circuit delay is increased by path-balancing, and we then raise a problem that performance optimization increases statisticallydistributed circuit delay. 1.

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We evaluate the effectiveness of statistical gate sizing to minimize circuit power. We develop reliable posynomial models for delay and power that are accurate to within 5-10 % of 130nm library data. We formulate statistical sizing as a geometric program, accounting for randomness in gate delays. For various ISCAS-85 circuits, statistical sizing at a 99.8% target yield provides 25 % power reduction compared to a 3σ worst-case deterministic approach. However, this can be replicated by deterministic sizing using a less conservative corner. Statistical sizing, under assumptions of variational independence, is still conservative and further power reductions can be achieved for the same timing target and yield. 1.

Assigning gate supply voltage and transistor threshold voltages to a range of discrete values is a combinatorial problem. The optimization computational difficulty grows exponentially with the netlist size. Whereas, if the range of values is continuous, we show that the global optimum can be found in polynomial time. We show that posynomials can model variable supply and threshold voltages, with skewed gate drive strengths. The models have root mean square (RMS) errors of 10 % or less compared to 0.13um SPICE data. With these models, geometric programming gives a convex problem formulation with globally optimal solutions for minimum delay, energy×delay, or power. For the examples considered, dual voltage and continuous voltage solutions reduce power by up to 22 % compared to the optimal solution using single supply and thresholds voltages. 1.