A semi-custom high-speed datapath design flow is described using commercial ASIC design CAD tools interacting with a simple hierarchical placement Matlab code. The flow leverages the vast automation and verification capabilities of ASIC design CAD tools, while providing a precision close to a fully custom-designed circuit. The methodology is applied to the design of a 4-channel, 3-GHz per-channel, digital equalizer for multitone high-speed backplane serial link applications. Each equalizer channel is a 16-tap, 10-bits per tap, linear FIR filter. The design is in a 90-nm CMOS technology and runs with a 1.5-GHz clock.

This paper describes a custom design method of ASICs with on-demand library generation. According to the result of performance estimation, a tailored library is generated and supplied to cell-based design tools. A symbolic layout system that produces a cell layout with variable driving strength is developed. The tunability can be utilized for generating a rich set of driving strength as well as design optimization in postlayout stage. Design experiments and measured performance of a fabricated chip demonstrate the effectiveness of the proposed approach.

Abstract. Physical Uncloneable Functions (PUF) are systems whose physical behavior to different inputs can be measured reliably, yet cannot be cloned in a physical replica. Existing designs propose to derive uncloneability from an assumed practical impossibility of exactly replicating inherent manufacturing variations, e.g., between individual chipset instances. The PUF promise has drawn significant attention lately and numerous researchers have proposed to use PUFs for various security assurances ranging from authentication to software licensing. In this paper we survey the history of PUFs as well as the existing body of research proposing applications thereof. 1

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This paper investigates subthreshold voltage operation of digital circuits. Starting from the previously known single supply voltage for minimum energy per cycle, we further lower the energy consumption by using dual subthreshold supplies. Level converters, commonly used in the above threshold design, are found to be unacceptably slow for subthreshold voltage operation. Therefore, special constraints are used to eliminate level converters. We give a new mixed integer linear program (MILP) that automatically and optimally assigns gate voltages, avoids the use of level converters, and holds the minimum critical path delay, while minimizing the total energy per cycle. Using examples of a 16-bit ripple-carry adder and a 4 × 4 multiplier we show energy savings of 23 % and 5%, respectively. The latter is a worst case example because most paths are critical. Alternatively, for the same energy as that of single below-threshold supply, an optimized dual voltage design can operate at 3 to 4 times higher clock rate. Also, we show energy saving up to 22.2 % from the minimum energy point over ISCAS’85 benchmark circuits. The MILP optimization with special consideration for level converters is general and applicable to any supply voltage range.