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Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation
 In Proceedings of the 1998 IEEE/ACM international conference on Computeraided design
, 1997
"... This paper considers simultaneous gate and wire sizing for general VLSI circuits under the Elmore delay model. We present a fast and exact algorithm which can minimize total area subject to maximum delay bound. The algorithm can be easily modified to give exact algorithms for optimizing several othe ..."
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Cited by 90 (8 self)
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This paper considers simultaneous gate and wire sizing for general VLSI circuits under the Elmore delay model. We present a fast and exact algorithm which can minimize total area subject to maximum delay bound. The algorithm can be easily modified to give exact algorithms for optimizing several other objectives (e.g. minimizing maximum delay or minimizing total area subject to arrival time specifications at all inputs and outputs). No previous algorithm for simultaneous gate and wire sizing can guarantee exact solutions for general circuits. Our algorithm is an iterative one with a guarantee on convergence to global optimal solutions. It is based on Lagrangian relaxation and "onegate/wireatatime" local optimizations, and is extremely economical and fast. For example, we can optimize a circuit with 13824 gates and wires in about 13 minutes using under 12 MB memory on an IBM RS/6000 workstation. 1 Introduction Since the invention of integrated circuits almost 40 years ago, gate si...
An InterconnectCentric Design Flow for Nanometer Technologies
 Proceedings of the IEEE
, 1999
"... As the IC devices is scaled into nanometer dimen sions and operates in gigahertz frequencies, interconnect design and optimization have become critical in determining the system performance and reliability. ..."
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Cited by 76 (26 self)
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As the IC devices is scaled into nanometer dimen sions and operates in gigahertz frequencies, interconnect design and optimization have become critical in determining the system performance and reliability.
Interconnect design for deep submicron ICs
 IN PROC. INT. CONF. ON COMPUTER AIDED DESIGN
, 1997
"... Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of interconnect design as the technology feature size rapidly decreases towards below 0.1 micron. Then, we ..."
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Cited by 72 (22 self)
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Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of interconnect design as the technology feature size rapidly decreases towards below 0.1 micron. Then, we present commonly used interconnect models and a set of interconnect design and optimization techniques for improving interconnect performance and reliability. Finally, we present comparisons of different optimization techniques in terms of their efficiency and optimization results, and show the impact of these optimization techniques on interconnect performance in each technology generation from the 0.35µm to 0.07µm projected in the National Technology Roadmap for Semiconductors.
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
 IN PROC. INT. SYMP. ON PHYSICAL DESIGN
, 1997
"... In this paper, we consider the delay minimization problem of a wire by simultaneously considering buffer insertion, buffer sizing and wire sizing. We consider three versions of the problem, namely using no buffer, using a given number of buffers, and using optimal number of buffers. We provide elega ..."
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Cited by 49 (5 self)
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In this paper, we consider the delay minimization problem of a wire by simultaneously considering buffer insertion, buffer sizing and wire sizing. We consider three versions of the problem, namely using no buffer, using a given number of buffers, and using optimal number of buffers. We provide elegant closed form optimal solutions for all these versions.
Optimal WireSizing Function with Fringing Capacitance Consideration
 Proc. ACM/IEEE Design Automation Conf
, 1997
"... In this paper, we consider nonuniform wiresizing under the Elmore delay model. Given a wiresegment of length L, let f#x# be the width of the wireatposition x, 0 # x #L. It was shown in #2, 5# that the optimal wiresizing function which minimizes delay is an exponential tapering function f#x ..."
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Cited by 23 (7 self)
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In this paper, we consider nonuniform wiresizing under the Elmore delay model. Given a wiresegment of length L, let f#x# be the width of the wireatposition x, 0 # x #L. It was shown in #2, 5# that the optimal wiresizing function which minimizes delay is an exponential tapering function f#x#=ae ,bx , where a#0and b#0areconstants. Unfortunately, #2, 5# did not consider fringing capacitance which is at least comparable in size to areacapacitancein deep submircon designs. As a result, exponential tapering is no longer the optimal strategy. In this paper, we show that the optimal wiresizing function, taking fringing capacitance into consideration, is f#x#= ,c f 2c 0 # 1 W# ,c f ae ,bx # +1# where W#x#= P 1 n=1 #,n# n,1 n! x n is the Lambert's W function, cf and c0 are the respective fringing capacitance and areacapacitance of wireper unit square, a#0and b#0areconstants. The optimal wiresizing function degenerates into an exponential tapering function as cf...
Shaping A VLSI Wire to Minimize Elmore Delay
, 1997
"... Euler's differential equation of the calculus of variations is used to determine the shape of a VLSI wire that minimizes Elmore delay. The solution is given as a power series whose coefficients are formulas involving the loadend wire width, the load capacitance, the capacitance per unit area, ..."
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Cited by 19 (0 self)
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Euler's differential equation of the calculus of variations is used to determine the shape of a VLSI wire that minimizes Elmore delay. The solution is given as a power series whose coefficients are formulas involving the loadend wire width, the load capacitance, the capacitance per unit area, and the capacitance per unit perimeter. In contrast to an optimalwidth rectangular wire, the RC Elmore delay of the optimally tapered wire goes to zero as the driver resistance goes to zero. The optimal taper is immune, to first order, to process variations affecting wire width.
A new approach to simultaneous buffer insertion and wire sizing
 PROC. INT. CONF. ON COMPUTER AIDED DESIGN
, 1997
"... In this paper, we present a completely new approach to the problem of delay minimization by simultaneous buffer insertion and wire sizing for a wire. We show that the problem can be formulated as a convex quadratic program, which is known to be solvable in polynomial time. Nevertheless, we explore s ..."
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Cited by 13 (4 self)
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In this paper, we present a completely new approach to the problem of delay minimization by simultaneous buffer insertion and wire sizing for a wire. We show that the problem can be formulated as a convex quadratic program, which is known to be solvable in polynomial time. Nevertheless, we explore some special properties of our problem and derive an optimal and very efficient algorithm to solve the resulting program. Given m buffers and a set of n discrete choices of wire width, the running time of our algorithm is O(mn²) and is independent of the wire length in practice. For example, an instance of 100 buffers and 100 choices of wire width can be solved in 3 seconds. Besides, our formulation is so versatile that it is easy to consider other objectives like wire area or power dissipation, or to add constraints to the solution. Also, wire capacitance lookup tables, or very general wire capacitance models which can capture area capacitance, fringing capacitance, coupling capacitance, etc. can be used.
A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing
 IEEE Trans. ComputerAided Design
, 1999
"... Abstract—In this paper, we present a completely new approach to the problem of delay minimization by simultaneous buffer insertion and wire sizing for a wire. We show that the problem can be formulated as a convex quadratic program, which is known to be solvable in polynomial time. Nevertheless, we ..."
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Cited by 12 (2 self)
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Abstract—In this paper, we present a completely new approach to the problem of delay minimization by simultaneous buffer insertion and wire sizing for a wire. We show that the problem can be formulated as a convex quadratic program, which is known to be solvable in polynomial time. Nevertheless, we explore some special properties of our problem and derive an optimal and very efficient algorithm modified active set method (MASM) to solve the resulting program. Given m buffers and a set of n discrete choices of wire width, the running time of our algorithm is O(mn 2) and is independent of the wire length in practice. For example, an instance of 100 buffers and 100 choices of wire width can be solved in 0.92 s. In addition, we extend MASM to consider simultaneous buffer insertion, buffer sizing, and wire sizing. The resulting algorithm MASMBS is again optimal and very efficient. For example, with six choices of buffer size and 10 choices of wire width, the optimal solution for a 15 000 m long wire can be found in 0.05 s. Besides, our formulation is so versatile that it is easy to consider other objectives like wire area or power dissipation, or to add constraints to the solution. Also, wire capacitance lookup tables, or very general wire capacitance models which can capture area capacitance, fringing capacitance, coupling capacitance, etc. can be used. Index Terms—Buffer insertion, buffer sizing, interconnect, optimization, performance optimization, physical design, quadratic programming. I.
Greedy wiresizing is linear time
 in Proc. Int. Symp. Physical Design
, 1998
"... Abstract—The greedy wiresizing algorithm (GWSA) has been experimentally shown to be very efficient, but no mathematical analysis on its convergence rate has ever been reported. In this paper, we consider GWSA for continuous wire sizing. We prove that GWSA converges linearly to the optimal solution, ..."
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Cited by 12 (2 self)
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Abstract—The greedy wiresizing algorithm (GWSA) has been experimentally shown to be very efficient, but no mathematical analysis on its convergence rate has ever been reported. In this paper, we consider GWSA for continuous wire sizing. We prove that GWSA converges linearly to the optimal solution, which implies that the run time of GWSA is linear with respect to the number of wire segments for any fixed precision of the solution. Moreover, we also prove that this is true for any starting solution. This is a surprising result because previously it was believed that in order to guarantee convergence, GWSA had to start from a solution in which every wire segment is set to the minimum (or maximum) possible width. Our result implies that GWSA can use a good starting solution to achieve faster convergence. We demonstrate this point by showing that the minimization of maximum delay and the minimization of area subject to maximum delay bound using Lagrangian relaxation can be sped up by more than 50%. Index Terms — Interconnect, performance optimization, wiresizing. I.
An efficient and optimal algorithm for simultaneous buffer and wire sizing
 IEEE Trans. ComputerAided Design
, 1999
"... Abstract—In this paper, we consider the problem of interconnect delay minimization by simultaneous buffer and wire sizing under the Elmore delay model. We first present a polynomial time algorithm SBWS to minimize the delay of an interconnect wire. Previously, no polynomial time algorithm for the pr ..."
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Cited by 11 (0 self)
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Abstract—In this paper, we consider the problem of interconnect delay minimization by simultaneous buffer and wire sizing under the Elmore delay model. We first present a polynomial time algorithm SBWS to minimize the delay of an interconnect wire. Previously, no polynomial time algorithm for the problem has been reported in the literature. SBWS is an iterative algorithm with guaranteed convergence to the optimal solution. It runs in quadratic time and uses constant memory for computation. Experimental results show that SBWS is extremely efficient in practice. For example, for an interconnect of 10 000 segments and buffers, the CPU time is only 0.255 s. We then extend our result to handle interconnect trees. We present an algorithm SBWST which always gives the optimal solution. Experimental results show that SBWST is faster than the greedy wire sizing algorithm [2] in practice. Index Terms — Buffer sizing, interconnect, performance optimization, physical design, wire sizing.