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A new modular division algorithm and applications
 in Proc. of the 6th Int. Conf. on Theoretical Computer Science (ICTCS’98), World Scientific
, 1998
"... The present paper proposes a new parallel algorithm for the modular division u/v mod βs, where u, v, β and s are positive integers (β ≥ 2). The algorithm combines the classical addandshift multiplication scheme with a new propagation carry technique. This “Pen and Paper Inverse ” (PPI) algorithm, ..."
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The present paper proposes a new parallel algorithm for the modular division u/v mod βs, where u, v, β and s are positive integers (β ≥ 2). The algorithm combines the classical addandshift multiplication scheme with a new propagation carry technique. This “Pen and Paper Inverse ” (PPI) algorithm, is better suited for systolic parallelization in a “leastsignificant digit first ” pipelined manner. Although it is equivalent to Jebelean’s modular division algorithm [5] in terms of performance (time complexity, work, efficiency), the linear parallelization of the PPI algorithm improves on the latter when the input size is large. The parallelized versions of the PPI algorithm leads to various applications, such as the exact division and the digit modulus operation (dmod) of two long integers. It is also applied to the determination of the periods of rational numbers as well as their padic expansion in any radix β ≥ 2.
Two Binary Algorithms for Calculating the Jacobi Symbol and a Fast Systolic Implementation in Hardware
"... AbstractEfficiently computing the Jacobi symbol J ( a, b) for integers a and b is an important step in a number of cryptographic processes. We present two algorithms for computing J ( a, b) which can easily be implemented in hardware and which are efficient with respect to time and space. The firs ..."
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AbstractEfficiently computing the Jacobi symbol J ( a, b) for integers a and b is an important step in a number of cryptographic processes. We present two algorithms for computing J ( a, b) which can easily be implemented in hardware and which are efficient with respect to time and space. The first algorithm we describe is slower but also easier to implement in hardware than the second. The algorithms are systolic and thus each can be implemented as an array of identical cells. We have developed VHDL descriptions of these algorithms, and we provide here example code for the process statements which are central to the implementation of each algorithm. Each algorithm has been tested on an Altera Cyclone EP1C6Q240 device and simulated on an Altera StratixII EP2S15F484C3 device.