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There is reason to believe bounded aggressive processing (limiting the degree to which processes act on conditional knowledge) may be a good alternative to unbounded processing. Simulations characterized by substantial variance in logical process processing times can lead to conditions where, without bound, some processes may cause frequent repairs (e.g. rollbacks) to occur. We present an algorithm, SRADS/LR, in which we bound aggressiveness and discuss its expected impact on performance.

As massively parallel computers proliferate, there is growing interest in �nding ways by which performance of massively parallel codes can be e�ciently predicted. This problem arises in diverse contexts such as parallelizing compilers, parallel performance monitoring, and parallel algorithm development. In this paper we describe one solution where one directly executes the application code, but uses a discrete-event simulator to model details of the presumed parallel machine, such as operating system and communication network behavior. Because this approach is computationally expensive, we are interested in its own parallelization, speci�cally the parallelization of the discrete-event simulator. We describe methods suitable for parallelized direct execution simulation of message-passing parallel programs, and report on the performance of such a system, LAPSE �Large Application Parallel Simulation Environment�, wehave built on the Intel Paragon. On all codes measured to date, LAPSE predicts performance well, typically within 10 � relative error. Depending on the nature of the application code, we have observed low slowdowns �relative to natively executing code � and high relative speedups using up to 64 processors.

This paper describes an approach to discrete event simulation modeling that appears to be effective for developing portable and efficient parallel execution of models of large distributed systems and communication networks. In this approach, the modeler develops sub-models with an existing sequential simulation modeling tool, using the full expressive power of the tool. A set of modeling language extensions permit automatically synchronized communication between sub-models; however, the automation requires that any such communication must take a non-zero amount of simulation time. Within this modeling paradigm, a variety of conservative synchronization protocols can transparently support conservative execution of sub-models on potentially different processors. A specific implementation of this approach, U.P.S. (Utilitarian Parallel Simulator), is described, along with performance results on the Intel Paragon and on the IBM SP2. Portions of this paper are reproduced with permission fr...

As massively parallel computers become increasingly available, users' interest in the scalability of their parallel codes is growing. However, such computers are in high demand, and access to them is restricted. In this paper we develop techniques that allow one to use a small number of parallel processors to simulate the behavior of a message-passing code running on a large number of processors. Such methods will allow a user to performance tune a code for massive parallelism before actually using large numbers of processors. Other potential applications include parallel simulation of large distributed systems driven by directly executing application code, and high-performance simulations of network designs driven by directly executing application code. We distribute simulation processes and application processes among multitasking processors. Calls by application processes to message-passing routines are trapped by simulator processes, which are responsible for scheduling a...

This paper describes our approach to interoperability as well as an implementation of the backplane. We present results that demonstrate the proper operation of the backplane by distributing a network simulation between two different simulation packages, ns2 developed at USC/ISI and GloMoSim developed at UCLA. We present performance results that show that the overhead for the creation of the dynamic messages is minimal. Although this work is specific to network simulations, we believe our methodology and approach can be used to achieve interoperability in other distributed computing applications as well. 1

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This paper describes an approach to discrete event simulation modeling that appears to be e�ective for developing portable and e�cient parallel execution of models of large distributed systems and communication networks. In this approach, the modeler develops sub-models using an existing sequential simulation modeling tool, using the full expressive power of the tool. A set of modeling language extensions permit automatically synchronized communication between sub-models; however, the automation requires that any such communication must take a non-zero amount of simulation time. Within this modeling paradigm, a variety of conservative synchronization protocols can transparently support conservative execution of sub-models on potentially di�erent processors. A speci�c implementation of this approach, U.P.S. �Utilitarian Parallel Simulator�, is described, along with performance results on the

Timed Petri-nets are used to model numerous types of large complex systems, especially computer architectures and communication networks. While formal analysis of such models is sometimes possible, discrete-event simulation remains the most general technique available for assessing the model's behavior. However, simulation's computational requirements can be massive, especially on the large complex models that defeat analytic methods. One way of meeting these requirements is by executing the simulation on a parallel machine. This paper describes simple techniques for the automated parallelization of timed Petri-net simulations. We address both the issue of processor synchronization, as well as the automated mapping, static and dynamic, of the Petri-net to the parallel architecture. As part of this effort we describe a new mapping algorithm, one that also applies to more general parallel computations. We establish analytic properties of the solution produced by the algorithm, including ...

It has been established elsewhere [Reyn92] that hardware to support parallel discrete event simulations (PDES) is desirable. We describe the steps leading to the implementation of a hardware-based framework to support PDES. We begin with an exploration of the criteria necessary to make such a framework both practical and useful, concluding that maintenance of sequential consistency is sufficient, while "observable" sequential consistency is more desirable but difficult to attain. We derive a functional design based on these criteria, and from that derive a prototype design. Also, we establish the utility of our design, showing that computation of critical global values, such as global virtual time, can be done in times two orders of magnitude or better than typical event times in discrete event simulations. ############################################################################################## 1. Introduction The need for special purpose hardware to support efficient parallel d...