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45
An EndtoEnd Systems Approach to Elliptic Curve Cryptography
 In Cryptographic Hardware and Embedded Systems (CHES
, 2002
"... Since its proposal by Victor Miller [17] and Neal Koblitz [15] in the mid 1980s, Elliptic Curve Cryptography (ECC) has evolved into a mature publickey cryptosystem. Offering the smallest key size and the highest strength per bit, its computational efficiency can benefit both client devices and serv ..."
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Cited by 26 (3 self)
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Since its proposal by Victor Miller [17] and Neal Koblitz [15] in the mid 1980s, Elliptic Curve Cryptography (ECC) has evolved into a mature publickey cryptosystem. Offering the smallest key size and the highest strength per bit, its computational efficiency can benefit both client devices and server machines. We have designed a programmable hardware accelerator to speed up point multiplication for elliptic curves over binary polynomial fields GF (2^m). The accelerator is based on a scalable architecture capable of handling curves of arbitrary field degrees up to m = 255. In addition, it delivers optimized performance for a set of commonly used curves through hardwired reduction logic. A prototype implementation running in a Xilinx XCV2000E FPGA at 66.4 MHz shows a performance of 6987 point multiplications per second for GF(2^163). We have integrated ECC into OpenSSL, today's dominant implementation of the secure Internet protocol SSL, and tested it with the Apache web server and opensource web browsers.
Reconfigurable computing: architectures and design methods
 IEE Proceedings  Computers and Digital Techniques
, 2005
"... Abstract: Reconfigurable computing is becoming increasingly attractive for many applications. This survey covers two aspects of reconfigurable computing: architectures and design methods. The paper includes recent advances in reconfigurable architectures, such as the Alters Stratix II and Xilinx Vir ..."
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Cited by 22 (3 self)
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Abstract: Reconfigurable computing is becoming increasingly attractive for many applications. This survey covers two aspects of reconfigurable computing: architectures and design methods. The paper includes recent advances in reconfigurable architectures, such as the Alters Stratix II and Xilinx Virtex 4 FPGA devices. The authors identify major trends in generalpurpose and specialpurpose
A Cryptographic Processor for Arbitrary Elliptic Curves over GF(2 m
, 2003
"... We describe a cryptographic processor for Elliptic Curve Cryptography (ECC). ECC is evolving as an attractive alternative to other publickey cryptosystems such as the RivestShamirAdleman algorithm (RSA) by offering the smallest key size and the highest strength per bit. The cryptographic processo ..."
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Cited by 20 (3 self)
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We describe a cryptographic processor for Elliptic Curve Cryptography (ECC). ECC is evolving as an attractive alternative to other publickey cryptosystems such as the RivestShamirAdleman algorithm (RSA) by offering the smallest key size and the highest strength per bit. The cryptographic processor performs point multiplication for elliptic curves over binary polynomial fields GF(2 m). In contrast to other designs that only support one curve at a time, our processor is capable of handling arbitrary curves without requiring reconfiguration. More specifically, it can handle both named curves as standardized by the National Institute for Standards and Technology (NIST) as well as any other generic curves up to a field degree of 255. Efficient support for arbitrary curves is particularly important for the targeted server applications that need to handle requests for secure connections generated by a multitude of heterogeneous client devices. Such requests may specify curves which are infrequently used or not even known at implementation time. We have implemented the cryptographic processor in a fieldprogrammable gate array (FPGA) running at a clock frequency of 66.4 MHz. Its performance is 6955 point multiplications per
Genus Two Hyperelliptic Curve Coprocessor
 In Workshop on Cryptographic Hardware and Embedded Systems  CHES 2002
, 2002
"... Abstract. Hyperelliptic curve cryptography with genus larger than one has not been seriously considered for cryptographic purposes because many existing implementations are significantly slower than elliptic curve versions with the same level of security. In this paper, the first ever complete hardw ..."
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Cited by 19 (0 self)
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Abstract. Hyperelliptic curve cryptography with genus larger than one has not been seriously considered for cryptographic purposes because many existing implementations are significantly slower than elliptic curve versions with the same level of security. In this paper, the first ever complete hardware implementation of a hyperelliptic curve coprocessor is described. This coprocessor is designed for genus two curves over F 2 113. Additionally, a modification to the Extended Euclidean Algorithm is presented for the GCD calculation required by Cantor’s algorithm. On average, this new method computes the GCD in onefourth the time required by the Extended Euclidean Algorithm. 1
A reconfigurable system on chip implementation for elliptic curve cryptography over GF(2^n)
, 2002
"... The performance of elliptic curve based public key cryptosystems is mainly appointed by the efficiency of the underlying finite field arithmetic. This work describes two generic and scalable architectures of finite field coprocessors, which are implemented within the latest family of Field Programm ..."
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Cited by 18 (0 self)
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The performance of elliptic curve based public key cryptosystems is mainly appointed by the efficiency of the underlying finite field arithmetic. This work describes two generic and scalable architectures of finite field coprocessors, which are implemented within the latest family of Field Programmable System Level Integrated Circuits FPSLIC from Atmel, Inc. The HW architectures are adapted from Karatsuba’s divide and conquer algorithm and allow for a reasonable speedup of the toplevel elliptic curve algorithms. The VHDL hardware models are automatically generated based on an eligible operand size, which permits the optimal utilization of a particular FPSLIC device.
Reconfigurable Implementation of Elliptic Curve Crypto Algorithms
 RECONFIGURABLE ARCHITECTURES WORKSHOP, 16TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM
, 2002
"... For FPGA based coprocessors for elliptic curve cryptography, a significant performance gain can be achieved when hybrid coordinates are used to represent points on the elliptic curve. We provide a new area/performance tradeoff analysis of different hybrid representations over fields of characteristi ..."
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Cited by 13 (0 self)
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For FPGA based coprocessors for elliptic curve cryptography, a significant performance gain can be achieved when hybrid coordinates are used to represent points on the elliptic curve. We provide a new area/performance tradeoff analysis of different hybrid representations over fields of characteristic two. Moreover, we present a new generic cryptoprocessor architecture that can be adapted to various area/performance constraints and finite field sizes, and show how to apply high level synthesis techniques to the controller design.
FPGA Accelerated Tate Pairing Based Cryptosystems over Binary Fields
 IN CRYPTOLOGY EPRINT ARCHIVE, REPORT 2006/179
, 2006
"... Though the implementation of the Tate pairing is commonly believed to be computationally more intensive than other cryptographic operations, such as ECC point multiplication, there has been a substantial progress in speeding up the Tate pairing computations. Because of their inherent parallelism, ..."
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Cited by 12 (0 self)
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Though the implementation of the Tate pairing is commonly believed to be computationally more intensive than other cryptographic operations, such as ECC point multiplication, there has been a substantial progress in speeding up the Tate pairing computations. Because of their inherent parallelism, the existing Tate pairing algorithms are very suitable for hardware implementation aimed at achieving a high operation speed. Supersingular elliptic curves over binary fields are good candidates for hardware implementation due to their simple underlying algorithms and binary arithmetic. In this paper we propose e#cient Tate pairing implementations over binary fields F 2 239 and F 2 283 via FPGA. Though our field sizes are larger than those used in earlier architectures with the same security strength based on cubic elliptic curves or binary hyperelliptic curves, fewer multiplications in the underlying field are required, so that the computational latency for one pairing can be reduced. As a result, our pairing accelerators implemented via FPGA can run 15to25 times faster than other FPGA realizations at the same level of security strength, and at the same time achieve lower product of latency by area.
Ultra High Performance ECC over NIST Primes on Commercial FPGAs
 In Proceedings of CHES
, 2008
"... Abstract. Elliptic Curve Cryptosystems (ECC) have gained increasing acceptance in practice due to their significantly smaller bit size of the operands compared to other publickey cryptosystems. Since their computational complexity is often lower than in the case of RSA or discrete logarithm schemes ..."
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Cited by 12 (5 self)
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Abstract. Elliptic Curve Cryptosystems (ECC) have gained increasing acceptance in practice due to their significantly smaller bit size of the operands compared to other publickey cryptosystems. Since their computational complexity is often lower than in the case of RSA or discrete logarithm schemes, ECC are often chosen for high performance publickey applications. However, despite a wealth of research regarding highspeed software and highspeed FPGA implementation of ECC since the mid 1990s, providing truly highperformance ECC on readily available (i.e., nonASIC) platforms remains an open challenge. This holds especially for ECC over prime fields, which are often preferred over binary fields due to standards in Europe and the US. This work presents a new architecture for an FPGAbased ultra high performance ECC implementation over prime fields. Our architecture makesintensiveuseoftheDSPblocksinmodernFPGAs,whichare embedded arithmetic units actually intended to accelerate digital signal processing algorithms. We describe a novel architecture and algorithms for performing ECC arithmetic and describe the actual implementation of standard compliant ECC based on the NIST primes P224 and P256. We show that ECC on Xilinx’s Virtex4 SX55 FPGA can be performed at a rate of more than 37,000 point multiplications per second. Our architecture outperforms all singlechip hardware implementations over prime fields in the open literature by a wide margin.
High Performance Architecture of Elliptic Curve Scalar Multiplication
 Scalar Multiplication, CACR Research Report
, 2006
"... A high performance architecture of elliptic curve scalar multiplication over finite field GF(2 m) is proposed. A pseudopipelined word serial finite field multiplier with word size w, suitable for the scalar multiplication is also developed. Implemented in hardware, this system performs a scalar mul ..."
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Cited by 11 (0 self)
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A high performance architecture of elliptic curve scalar multiplication over finite field GF(2 m) is proposed. A pseudopipelined word serial finite field multiplier with word size w, suitable for the scalar multiplication is also developed. Implemented in hardware, this system performs a scalar multiplication in approximately 6⌈m/w⌉(m − 1) clock cycles and the gate delay in the critical path is equal to TAND + (log 2 w)TXOR, where TAND and TXOR are delays due to twoinput AND and XOR gates respectively. Index Terms Scalar multiplication, elliptic curves, finite fields