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Reconfigurable computing: architectures and design methods.”
 Proceedings on IEEE Computers and Digital Techniques,
, 2005
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Wordlength optimization for linear digital signal processing
 IEEE Trans. ComputerAided Design of Integrated Circuits and Systems
, 2003
"... Abstract—This paper presents an approach to the wordlength allocation and optimization problem for linear digital signal processing systems implemented as custom parallel processing units. Two techniques are proposed, one which guarantees an optimum set of wordlengths for each internal variable, and ..."
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Cited by 38 (12 self)
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Abstract—This paper presents an approach to the wordlength allocation and optimization problem for linear digital signal processing systems implemented as custom parallel processing units. Two techniques are proposed, one which guarantees an optimum set of wordlengths for each internal variable, and one which is a heuristic approach. Both techniques allow the user to tradeoff implementation area for arithmetic error at system outputs. Optimality (with respect to the area and error estimates) is guaranteed through modeling as a mixed integer linear program. It is demonstrated that the proposed heuristic leads to area improvements of 6 % to 45 % combined with speed increases compared to the optimum uniform wordlength design. In addition, the heuristic reaches within 0.7% of the optimum multiple wordlength area over a range of benchmark problems. Index Terms—Bitwidth, digital signal processor (DSP), optimization, precision, wordlength.
R.: Encoding OCL Data Types for SATBased Verification of UML/OCL Models
 TAP. Lecture
"... Abstract. Checking the correctness of UML/OCL models is a crucial task in the design of complex software and hardware systems. As a consequence, several approaches have been presented which address this problem. Methods based on satisfiability (SAT) solvers have been shown to be very promising in t ..."
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Cited by 11 (3 self)
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Abstract. Checking the correctness of UML/OCL models is a crucial task in the design of complex software and hardware systems. As a consequence, several approaches have been presented which address this problem. Methods based on satisfiability (SAT) solvers have been shown to be very promising in this domain. Here, the actual verification task is encoded as an equivalent bitvector instance to be solved by an appropriate solving engine. However, while a bitvector encoding for basic UML/OCL constructs has already been introduced, no encoding for nontrivial OCL data types and operations is available so far. In this paper, we close this gap and present a bitvector encoding for more complex OCL data types, i.e. sets, bags, and their ordered counterparts. As a result, SATbased UML/OCL verification becomes applicable for models containing these collections types. A case study illustrates the application of this encoding. 1
A Compact DSP Core with Static FloatingPoint Arithmetic
 The Journal of VLSI Signal Processing System
, 2006
"... The multimedia SoC usually integrates programmable digital signal processors (DSP) to accelerate dataintensive computations. But the DSP and the host processor (e.g. ARM) are both designed for standalone uses, and they must have overlapped functionalities and thus some redundant components. In this ..."
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Cited by 2 (0 self)
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The multimedia SoC usually integrates programmable digital signal processors (DSP) to accelerate dataintensive computations. But the DSP and the host processor (e.g. ARM) are both designed for standalone uses, and they must have overlapped functionalities and thus some redundant components. In this paper, we propose a compact DSP core for dualcore multimedia SoC and its complete software development tools. The DSP core contains a dataflow engine that is composed of offtheshelf memory modules with limited ports, and we have investigated software techniques extensively to reduce the hardware complexity as the principles of VLIW processors. Moreover, the DSP is equipped with novel static floatingpoint units to emulate expensive floatingpoint DSP operations at low cost. In our experiments, this core has about thrice the performance (estimated in execution cycles) of Analog Devices ADSP218x with similar computing resources. Our first prototype in the 0.35µm CMOS technology operates at 100MHz and consumes 122mW power. The core size is 2.8mm 2 including an embedded DMA controller and the AMBA AHB interface.
Finding Linear BuildingBlocks for RTL Synthesis of Polynomial Datapaths with FixedSize BitVectors
"... Polynomial computations over fixedsize bitvectors are found in many practical datapath designs. For efficient RTL synthesis, it is important to identify good decompositions of the polynomial into smaller/simpler units. Symbolic computer algebra algorithms and tools have been used for this purpose. ..."
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Polynomial computations over fixedsize bitvectors are found in many practical datapath designs. For efficient RTL synthesis, it is important to identify good decompositions of the polynomial into smaller/simpler units. Symbolic computer algebra algorithms and tools have been used for this purpose. However, fixedsize (m) bitvector arithmetic is polynomial algebra over the finite integer ring Z2 m, which is a nonunique factorization domain (nonUFD). While nonUFDs provide an extra freedom to search for decompositions, they complicate polynomial manipulation as traditional divisionbased algorithms are inapplicable. This paper presents new mathematical concepts for polynomial decomposition over Z2m, for RTL synthesis over fixedsize mbit vectors. Given a polynomial, we identify a specific set of linear expressions and compute the Gröbner bases of their ideal (over nonUFD Z2m) using syzygies. This basis serves as good buildingblocks for the given computation. A decomposition is identified by subsequent Gröbner basis reduction. Experimental results demonstrate significant area savings due to our approach, as compared against contemporary datapath synthesis techniques.
Contents lists available at SciVerse ScienceDirect Digital Signal Processing
"... www.elsevier.com/locate/dsp Reconfigurable FPGAbased switching path frequencydomain echo canceller with ..."
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www.elsevier.com/locate/dsp Reconfigurable FPGAbased switching path frequencydomain echo canceller with
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"... IOS Press Using type analysis in compiler to mitigate integeroverflowtobufferoverflow threat ..."
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IOS Press Using type analysis in compiler to mitigate integeroverflowtobufferoverflow threat
DOI: 10.1007/s1126500541785 A Compact DSP Core with Static FloatingPoint Arithmetic∗
, 2004
"... Abstract. A multimedia systemonachip (SoC) usually contains one or more programmable digital signal processors (DSP) to accelerate dataintensive computations. But most of these DSP cores are designed originally for standalone applications, and they must have some overlapped (and redundant) comp ..."
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Abstract. A multimedia systemonachip (SoC) usually contains one or more programmable digital signal processors (DSP) to accelerate dataintensive computations. But most of these DSP cores are designed originally for standalone applications, and they must have some overlapped (and redundant) components with the host microprocessor. This paper presents a compact DSP for multicore systems, which is fully programmable and has been optimized to execute a set of signal processing kernels very efficiently. The DSP core was designed concurrently with its automatic software generator based on highlevel synthesis. Moreover, it performs lightweight arithmetic—the static floatingpoint (SFP), which approximates the quality of floatingpoint (FP) operations with the hardware similar to that of the integer arithmetic. In our simulations, the compact DSP and its autogenerated software can achieve 3X performance (estimated in cycles) of those DSP cores in the dualcore baseband processors with similar computing resources. Besides, the 16bit SFP has above 40 dB signal to roundoff noise ratio over the IEEE singleprecision FP, and it even outperforms the handoptimized programs based on the 32bit integer arithmetic. The 24bit SFP has above 64 dB quality, of which the maximum precision is identical to that of the singleprecision FP. Finally, the DSP core has been implemented and fabricated in the UMC 0.18µm 1P6M CMOS technology. It can operate at 314.5 MHz while consuming 52mW average power. The core size is only 1.5 mm×1.5 mm including the 16 KB onchip memory and the AMBA AHB interface. 1.