This paper introduces GRASP (Generic seaRch Algorithm for the Satisjiability Problem), an integrated algorithmic framework for SAT that un.$es several previously proposed searchpruning techniques and facilitates ident$cation of additional ones. GRASP is premised on the inevitability of confzicts during search and its most distinguishing feature is the augmentation of basic backtracking search with a powerfil confzict analysis procedure. Analyzing confzicts to determine their cawes enables GRASP to backtrack non-chronologically to earlier levels in the search tree, potentially pruning large portions of the search space. In addition, by “recording ” the causes of conflicts, GRASP can recognize andpreempt the occurrence of similar conficts later on in the search. Finally, straightjwward bookkeeping of the causality chains leading up to conflicts allows GRASP to identifi assignments that are necessary for a solution to be found. fiperimental results obtained from a large number of benchmarks, including many from the $eld of test pattern generation, indicate that application of the proposed confzict analysis techniques to SATalgorithm can be extremely effectivefor a large number of representative classes of SAT instances. 1

This paper presents new techniques for speeding up deterministic test pattern generation for VLSI circuits. These techniques improve the PODEM algorithm by reducing number of backtracks with a low computational cost. This is achieved by finding more necessary signal line assignments, by detecting conflicts earlier, and by avoiding unnecessary work during test generation. We have incorporated these techniques into an advanced ATPG system for combinational circuits, called ATOM. The performance results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits demonstrated the effectiveness of these techniques on the test generation performance. ATOM detected all the testable faults and proved all the redundant faults to be redundant with a small number of backtracks in a short amount of time. 1 Introduction As the complexity of VLSI circuits and their quality requirements are increasing, the problem of test generation is becoming more important. Since the scan-based desig...

In recent years several highly effective algorithms have been proposed for Automatic Test Pattem Generation (ATPG). Nevertheless, most of these algorithms too ojien rely on different types of heuristics to achieve good empir-ical performance. Moreovel; there has not been signgcant research work on developing algorithms that are robust, in the sense that they can handle most faults with little heu-ristic guidance. In this paper we describe an algorithm for ATPG that is robust and still very efficient. In contrast with existing algorithms for ATPG, the proposed algo-rithm reduces heuristic knowledge to a minimum and relies on an optimized search algorithm for effectively pruning the search space. Even though the experimental results are obtained using an ATPG tool built on top of a Propositional Satisfability (SAT) algorithm, the same con-cepts can be integrated on application-speciJc algorithms. 1

This paper addresses the problem of test pattern generation for single stuck-at faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized. This problem has different applications in testing, including the identification of don't care conditions to be used in the synthesis of Built-In Self-Test (BIST) logic. The proposed solution is based on an integer linear programming (ILP) formulation which builds on an existing Propositional Satisfiability (SAT) model for test pattern generation. The resulting ILP formulation is linear on the size of the original SAT model for test generation, which is linear on the size of the circuit. Nevertheless, the resulting ILP instances represent complex optimization problems, that require dedicated ILP algorithms. Preliminary results on benchmark circuits validate the practical applicability of the test pattern minimization model and associated ILP algorithm

This paper addresses the problem of test pattern generation for single stuck-at faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized. This problem has different applications in testing, including the identification of don't care conditions to be used in the synthesis of Built-In Self-Test (BIST) logic. The proposed solution is based on an integer linear programming (ILP) formulation which builds on an existing Propositional Satisfiability (SAT) model for test pattern generation. The resulting ILP formulation is linear on the size of the original SAT model for test generation, which is linear on the size of the circuit. Nevertheless, the resulting ILP instances represent complex optimization problems, that require dedicated ILP algorithms. Preliminary results on benchmark circuits validate the practical applicability of the test pattern minimization model and associated ILP algorithm. 1 Introduction Auto...

A high-level test generation algorithm SWIFT is proposed which incorporates a symbolic scheduling procedure, derived from high-level synthesis applications, to resolve decision conflicts during test generation. SWIFT uses the induced fault model to generate functional tests that guarantee detection of low-level structural faults. When applied to functional models of representative 74Xseries, ISCAS-85 and ISCAS-89 circuits, SWIFT produces test sequences that cover all gate-level stuck-at faults. Surprisingly, although they are derived from a high-level functional description of the circuit under test, most of these test sequences are of provably minimal or near-minimal size. 1 Introduction The goal of high-level test generation is to abstract lowlevel information about a circuit into a functional or highlevel form, thus reducing the effort needed to generate tests. Classical ATPG testing methods model circuits at the gate level [1], but due to the ever-increasing size of integrated ci...