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Robust search algorithms for test pattern generation
 in Proceedings of the FaultTolerant Computing Symposium
, 1997
"... In recent years several highly effective algorithms have been proposed for Automatic Test Pattem Generation (ATPG). Nevertheless, most of these algorithms too ojien rely on different types of heuristics to achieve good empirical performance. Moreovel; there has not been signgcant research work on d ..."
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Cited by 44 (13 self)
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In recent years several highly effective algorithms have been proposed for Automatic Test Pattem Generation (ATPG). Nevertheless, most of these algorithms too ojien rely on different types of heuristics to achieve good empirical performance. Moreovel; there has not been signgcant research work on developing algorithms that are robust, in the sense that they can handle most faults with little heuristic guidance. In this paper we describe an algorithm for ATPG that is robust and still very efficient. In contrast with existing algorithms for ATPG, the proposed algorithm reduces heuristic knowledge to a minimum and relies on an optimized search algorithm for effectively pruning the search space. Even though the experimental results are obtained using an ATPG tool built on top of a Propositional Satisfability (SAT) algorithm, the same concepts can be integrated on applicationspeciJc algorithms. 1
An exact solution to the minimum size test pattern problem
 in Proc. International Conference on Computer Design (ICCD
, 1998
"... This article addresses the problem of test pattern generation for single stuckat faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized. This problem has different applications in testing, including the identification of ..."
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Cited by 15 (0 self)
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This article addresses the problem of test pattern generation for single stuckat faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized. This problem has different applications in testing, including the identification of “don’t care ” conditions to be used in the synthesis of BuiltIn SelfTest (BIST) logic. The proposed solution is based on an integer linear programming (ILP) formulation which builds on an existing Propositional Satisfiability (SAT) model for test pattern generation. The resulting ILP formulation is linear on the size of the original SAT model for test generation, which is linear on the size of the circuit. Nevertheless, the resulting ILP instances represent complex optimization problems, that require dedicated ILP algorithms. Preliminary results on benchmark circuits validate the practical applicability of the test pattern minimization model and associated ILP algorithm.
Redundancy Identification Using Transitive Closure
 in Proc. of the 5th Asian Test Symp
, 1996
"... We analyze all signals of a combinational circuit simultaneously for redundancy. The state of a signal is represented by two binary variables. The first variable is the logic value of the signal. The second variable is the observability status of the signal with respect to all primary outputs. Boole ..."
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Cited by 11 (5 self)
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We analyze all signals of a combinational circuit simultaneously for redundancy. The state of a signal is represented by two binary variables. The first variable is the logic value of the signal. The second variable is the observability status of the signal with respect to all primary outputs. Boolean equations specify local relationships of these variables in a manner similar to the neural network or Boolean satisfiability method. All pairwise terms appearing in these Boolean equations are used to construct an implication graph, for which the transitive closure graph is obtained. Any signal assignments or relations found from the transitive closure are substituted into higherorder terms of the Boolean equations, some of which reduce to pairwise terms. Such cases are iteratively included in the transitive closure until no more reductions are possible. In the final transitive closure, all signals are examined for the following conditions of redundancy: (1) If a signal and its complement imply each other (contradiction) then both stuckat faults on that signal are redundant; (2) If one value implies the other value (fixation) then one of the stuckat faults on that signal is redundant; (3) If the true observability status of a signal implies its own false observability status, then both stuckat faults of that signal are redundant; (4) If a certain value of a signal implies the false observability status, then the corresponding stuckat fault is redundant. Despite the apparent similarities with the transitive closure based ATPG, the present method is quite different. Here transitive closure is computed just once, and not recomputed or updated separately for each fault as required in ATPG. We give ISCAS '85 benchmark results. For c6288, we could identify 31 out of 33 redu...
An Exact Solution to the MinimumSize Test Pattern Problem
 In Proceedings of the IEEE International Conference on Computer Design
, 1998
"... This paper addresses the problem of test pattern generation for single stuckat faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized. This problem has different applications in testing, including the identification of d ..."
Abstract

Cited by 7 (4 self)
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This paper addresses the problem of test pattern generation for single stuckat faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized. This problem has different applications in testing, including the identification of don't care conditions to be used in the synthesis of BuiltIn SelfTest (BIST) logic. The proposed solution is based on an integer linear programming (ILP) formulation which builds on an existing Propositional Satisfiability (SAT) model for test pattern generation. The resulting ILP formulation is linear on the size of the original SAT model for test generation, which is linear on the size of the circuit. Nevertheless, the resulting ILP instances represent complex optimization problems, that require dedicated ILP algorithms. Preliminary results on benchmark circuits validate the practical applicability of the test pattern minimization model and associated ILP algorithm. 1 Introduction Auto...
Testquality/cost optimization using outputdeviationbased reordering of test patterns
 IEEE Tran. on CAD
, 2008
"... Abstract—Atspeed functional testing, delay testing, and ndetection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too high; the 2005 International Roadmap for Semiconductors predicts that testapplication times will be 30 times lar ..."
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Cited by 5 (5 self)
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Abstract—Atspeed functional testing, delay testing, and ndetection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too high; the 2005 International Roadmap for Semiconductors predicts that testapplication times will be 30 times larger in 2010 than they are today. In addition, many new types of defects cannot be accurately modeled using existing fault models. Therefore, there is a need to model the quality of test patterns such that they can be quickly assessed for defect screening. Test selection is required to choose the most effective pattern sequences from large test sets. Current industry practice for test selection is based on fault grading, which is computationally expensive and must also be repeated for every fault model. Moreover, although efficient methods exist today, for faultoriented test generation, there is a lack of understanding on how best to combine the test sets thus obtained, i.e., derive the most effective union of the individual test sets without simply taking all the patterns for each fault model. This paper presents the use of the output deviation as a surrogate coveragemetric for pattern modeling and test grading. A flexible, but general, probabilisticfault model is used to generate a probability map for the circuit, which can subsequently be used for testpattern reordering. The output deviations resulting from the probability map(s) are used as a coveragemetric to model test patterns; the higher the deviation, the better the quality of the test pattern. We show that, for the ISCAS benchmark circuits and as compared to other reordering methods, the proposed method provides “steeper ” coverage curves for different fault models. Index Terms—Abortonfirstfail, defect coverage, testapplication time, testpattern grading, test selection. I.
A seedselection method to increase defect coverage for LFSRreseedingbased test compression
 in Proc. Eur. Test Symp., 2007
"... Abstract — LFSR reseeding forms the basis for many test compression solutions. A seed can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. Despite the availability of numerous LFSRreseedingbased compression methods in the literatu ..."
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Cited by 2 (2 self)
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Abstract — LFSR reseeding forms the basis for many test compression solutions. A seed can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. Despite the availability of numerous LFSRreseedingbased compression methods in the literature, relatively little is known about the effectiveness of these seeds for unmodeled defects. We use the recently proposed output deviation measure of the resulting patterns as a metric to select appropriate LFSR seeds. Experimental results are reported using test patterns for stuckat faults derived from selected seeds. These patterns achieve higher coverage for stuckopen and transition faults than patterns obtained using other methods. I.
DeviationBased LFSR Reseeding for TestData Compression
"... Abstract—Linear feedback shift register (LFSR) reseeding forms the basis for many testcompression solutions. A seed can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. Despite the availability of numerous LFSRreseedingbased comp ..."
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Abstract—Linear feedback shift register (LFSR) reseeding forms the basis for many testcompression solutions. A seed can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. Despite the availability of numerous LFSRreseedingbased compression methods in the literature, relatively little is known about the effectiveness of these seeds for unmodeled defects, particularly since there are often several candidate seeds for a test cube. We use the recently proposed output deviation measure of the resulting patterns as a metric to select appropriate LFSR seeds. Experimental results are reported using test patterns for stuckat and transition faults derived from selected seeds for the ISCAS89 and the IWLS05 benchmark circuits. These patterns achieve higher coverage for transition and stuckopen faults than patterns obtained using other seedgeneration methods for LFSR reseeding. Given a pattern pair (p1,p2) for transition faults, we also examine the transitionfault coverage for launch on capture by using p1 and p2 to separately compute output deviations. Results show that p1 tends to be better when there is a high proportion of donotcare bits in the test cubes, while p2 is a more appropriate choice when the transitionfault coverage is high. Index Terms—Defect coverage, linear feedback shift register (LFSR) reseeding, output deviation, seed selection, test compression. I.