There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the design of modern digital systems. Verification engineers can simulate hardware in order to verify its performance and correctness with help of an HDL. However, simulation can’t keep pace with the growth in size and complexity of circuits and has become a bottleneck of the design process. Distributed HDL simulation on a cluster of workstations has the potential to provide a cost-effective solution to this problem. In this paper, we describe the design and implementation of DVS, an object-oriented framework for distributed Verilog simulation. Verilog is an HDL which sees wide industrial use. DVS is an outgrowth of Clustered Time Warp, originally developed for logic simulation. The design of the framework emphasizes simplicity and extensibility and aims to accommodate experiments involving partitioning and dynamic load balancing. Preliminary results obtained by simulating a 16bit multiplier are presented.

this paper. The use of dynamic logic is attractive for synchronous designs but no dynamic gate standard cell libraries exist so far mostly due to the late input arrival, charge sharing and noise problems eliminated in GTL designs thanks to monotonic data transitions, completion detection and datadependent control

The paper presents Gate Transfer Level (GTL) as a general framework for synthesis of industrial complexity asynchronous quasi-delay-insensitive (QDI) circuits. The GTL flow automatically provides the finest degree of pipelining (gate-level) resulting in extremely high-performance designs. Automatic gate level pipelining is not possible for synchronous design due to the stage balance problem and clock related overheads (latches, clock skew and jitter). Experimental results show average 4.3x performance increase on MCNC benchmarks compared to synchronous RTL implementation. 1.

Abstract—As a consequence of Moore’s law, the size of integrated circuits has grown extensively, resulting in simulation becoming the major bottleneck in the circuit design process. On the other hand, parallel or distributed simulations can be applied as fast, feasible and cost effective approaches for correctness analysis of current VLSI circuits. In this paper, we developed the first Time Warp simulator which can simulate in parallel all synthesizable Verilog circuits. We observed 4,000,000 events per second on 32 processors for the Viterbi decoder with 800k gates. We also observed that the load of different processors differ by up to 12M events during the course of the simulation. As a result, we first develop two new dynamic load balancing approach which balance the load during the simulation. Afterward, we utilize reinforcement learning to create an algorithm which is a combination of the first two algorithms. We investigate the algorithms on gate level simulations of several open source VLSI circuits. Our results show up to a 25 % improvement in the simulation time using the reinforcement learning algorithm. To the best of our knowledge, this is the first time that reinforcement learning has been used for the dynamic load-balancing of Time Warp.

Abstract—In this paper, we describe a distributed dynamic load balancing algorithm for parallel optimistic gate level simulation. Our optimistic simulator is based on Time Warp. The load balancing algorithm makes decisions based on the processing and communication loads at each processor. At the core of the algorithm is a genetic algorithm which is used to determine the values of the tuning parameters associated with the algorithm. It also determines the size of the time window of the simulator. The time window is a mechanism used to control the level of optimism of an optimistic simulator in order to avoid excessive rollbacks. An important feature of the genetic algorithm is that it is on-line, i.e. it is executed during the course of the simulation. The genetic algorithm is executed in one processor while the other processors execute the simulation and the load balancing algorithm. Experimental results have indicated a significant decrease in the execution time of the simulation- up to a 70% decrease in the simulation time of an optimistic simulator.