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**1 - 3**of**3**### A Note on the Inversion Complexity of Boolean Functions in Boolean Formulas

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"... In this note, we consider the minimum number of NOT operators in a Boolean formula representing a Boolean function. In circuit complexity theory, the minimum number of NOT gates in a Boolean circuit computing a Boolean function f is called the inversion complexity of f. In 1958, Markov determined th ..."

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In this note, we consider the minimum number of NOT operators in a Boolean formula representing a Boolean function. In circuit complexity theory, the minimum number of NOT gates in a Boolean circuit computing a Boolean function f is called the inversion complexity of f. In 1958, Markov determined the inversion complexity of every Boolean function and particularly proved that ⌈log 2(n + 1) ⌉ NOT gates are sufficient to compute any Boolean function on n variables. As far as we know, no result is known for inversion complexity in Boolean formulas, i.e., the minimum number of NOT operators in a Boolean formula representing a Boolean function. The aim of this note is showing that we can determine the inversion complexity of every Boolean function in Boolean formulas by arguments based on the study of circuit complexity. 1

### Linear-Size Log-Depth Negation-Limited Inverter for k-tonic Binary Sequences

"... Abstract: A zero-one sequence x1,..., xn is k-tonic if the number of i’s such that xi � = xi+1 is at most k. The notion generalizes well-known bitonic sequences. In negation-limited complexity, one considers circuits with a limited number of NOT gates, being motivated by the gap in our understanding ..."

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Abstract: A zero-one sequence x1,..., xn is k-tonic if the number of i’s such that xi � = xi+1 is at most k. The notion generalizes well-known bitonic sequences. In negation-limited complexity, one considers circuits with a limited number of NOT gates, being motivated by the gap in our understanding of monotone versus general circuit complexity, and hoping to better understand the power of NOT gates. In this context, the study of inverters, i.e., circuits with inputs x1,..., xn and outputs ¬x1,..., ¬xn, is fundamental since an inverter with r NOTs can be used to convert a general circuit to one with only r NOTs. In particular, if linearsize log-depth inverter with r NOTs exists, we do not lose generality by only considering circuits with at most r NOTs when we seek superlinear size lower bounds or superlogarithmic depth lower bounds. Markov [JACM1958] showed that the minimum number of NOT gates necessary in an n-inverter is ⌈log 2(n + 1)⌉. Beals, Nishino, and Tanaka [SICOMP98–STOC95] gave a construction of an ninverter with size O(n log n), depth O(log n), and ⌈log 2(n + 1) ⌉ NOTs. We give a construction of circuits inverting k-tonic sequences with size O((log k) n) and depth O(log k log log n + log n) using log 2 n + log 2 log 2 log 2 n + O(1) NOTs. In particular, for the case where k = O(1), our k-tonic inverter achieves asymptotically optimal linear size and logarithmic depth. Our construction improves all the parameters of the k-tonic inverter by Sato, Amano, and Maruoka [CO-COON06] with size O(kn), depth O(k log 2 n), and O(k log n) NOTs. We also give a construction of k-tonic sorters achieving linear size and logarithmic depth with log 2 log 2 n+log 2 log 2 log 2 n+O(1) NOT gates for the case where k = O(1). The following question by Turán remains open: Is the size of any depth-O(log n) inverter with O(log n) NOT gates superlinear? Key Words: circuit complexity, negation-limited circuit, inverter, k-tonic 1

### Negation-Limited Complexity of Parity and Inverters

"... Abstract. We give improved lower bounds for the size of negationlimited circuits computing Parity and for the size of negation-limited inverters. An inverter is a circuit with inputs x1,...,xn and outputs ¬x1,...,¬xn. We show that (1) For n =2 r − 1, circuits computing Parity with r − 1 NOT gates ha ..."

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Abstract. We give improved lower bounds for the size of negationlimited circuits computing Parity and for the size of negation-limited inverters. An inverter is a circuit with inputs x1,...,xn and outputs ¬x1,...,¬xn. We show that (1) For n =2 r − 1, circuits computing Parity with r − 1 NOT gates have size at least 6n − log 2(n +1) − O(1) and (2) For n =2 r − 1, inverters with r NOT gates have size at least 8n − log 2 (n +1) − O(1). We derive our bounds above by considering the minimum size of a circuit with at most r NOT gates that computes Parity for sorted inputs x1 ≥ ·· · ≥ xn. For an arbitrary r, wecompletely determine the minimum size. For odd n, itis2n − r − 2for ⌈log 2(n +1)⌉−1 ≤ r ≤ n/2, and it is ⌊3/2 n⌋−1forr ≥ n/2. We also determine the minimum size of an inverter for sorted inputs with at most r NOT gates. It is 4n − 3r for ⌈log 2 (n +1)⌉≤r ≤ n. Inparticular, the negation-limited inverter for sorted inputs due to Fischer, which is a core component in all the known constructions of negation-limited inverters, is shown to have the minimum possible size. Our fairly simple lower bound proofs use gate elimination arguments. 1