Hwang and Li proposed the first remote user authentication scheme using smart cards to solve the problems of Lamport scheme. Unfortunately, Hwang and Li's scheme has some security weaknesses. First, Chan- Chang, Shen- Lin- Hwang and then Chang-Hwang pointed out some attacks on Hwang -- Li's scheme. This paper presents a new remote user authentication scheme with forward secrecy, which provides forward secrecy to the long term secret key of the authentication server. This scheme is also secure against Chan -- Cheng and all the extended attacks .

This paper presents abstract layout techniques for a variety of FPGA switch block architectures. We evaluate the relative density of subset, universal, and Wilton switch block architectures. For subset switch blocks of small size, we find the optimal implementations using a simple metric. We also develop a tractable heuristic that returns the optimal results for small switch blocks, and good results for large switch blocks. For switch blocks with general connectivity, we develop a representation and a layout evaluation technique. We use these techniques to compare a variety of small switch blocks. We find that the traditional Xilinx-style, subset switch block is superior to the other proposed architectures. Finally, we have hand-designed some small switch blocks to confirm our results.

ABSTRACT Goal-Directed Performance Tuning for Scientific Applications by Tien-Pao Shih Chair: Edward S. Davidson Performance tuning, as carried out by compiler designers and application programmers to close the performance gap between the achievable peak and delivered performance, becomes increasingly important and challenging as the microprocessor speeds and system sizes increase. However, although performance tuning on scientific codes usually deals with relatively small program regions, it is not generally known how to establish a reasonable performance objective and how to efficiently achieve this objective. We suggest a goal-directed approach and develop such an approach for each of three major system performance components: central processor unit (CPU) computation, memory accessing, and communication. For the CPU, we suggest using a machine-application performance model that characterizes workloads on four key function units (memory, floating-point, issue, and a virtual "dependence unit") to produce an upper bound performance objective, and derive a mechanism to approach this objective. A case study shows an average 1.79x speedup achieved by using this approach for the Livermore Fortran Kernels 1-12 running on the IBM RS/6000. For memory, as compulsory and capacity misses are relatively easy to characterize, we derive a method for building application-specific cache behavior models that report the number of misses for all three types of conflict misses: self, cross, and ping-pong. The method uses averaging concepts to determine the expected number of cache misses instead of attempting to count them exactly in each instance, which provides a more rapid, yet realistic assessment of expected cache behavior. For each type of conflict miss, we propose a reduction method that uses one or a combination of three techniques based on modifying or exploiting data layout: array padding, initial address adjustment, and access resequencing.

PVS (Prototype Verification System) is a mechanized framework for formal specification and interactive proof development. The PVS specification language is based on higher-order logic enriched with features such as predicate subtypes, dependent types, recursive datatypes, and parametric theories. Subtyping is a central concept in the PVS type system. PVS admits the definition of subtypes corresponding to nonzero integers, prime numbers, injective maps, order-preserving maps, and even empty subtypes. We examine the principles underlying the PVS subtype mechanism and its implementation and use. The PVS specification language is primarily a medium for communicating formal mathematical descriptions. Formal PVS specifications are meant for both mach...

Four-dimensional twisted group lattices are used as models for spacetime structure. Compared to other attempts at space-time deformation, they have two main advantages: They have a physical interpretation and there is no difficulty in putting field theories on these structures. We present and discuss ordinary and gauge theories on twisted group lattices. We solve the free field theory case by finding all the irreducible representations. The non-abelian gauge theory on the two-dimensional twisted group lattice is also solved. On twisted group lattices, continuous space-time translational and rotational symmetries are replaced by discrete counterparts. We discuss these symmetries in detail. Four-dimensional twisted group lattices can also be used as models for non-trivial discrete compactifactions of certain ten-dimensional spaces.

Our goal is to implement a program for the machine verification of textbook proofs. We study the task from both the linguistics and automated reasoning perspective and give an in-depth analysis for a sample textbook proof. We propose a framework for natural language proof understanding that extends and integrates state-of-the-art technologies from Natural Language Processing (Discourse Representation Theory) and Automated Reasoning (Proof Planning) in a novel and promising way, having the potential to initiate progress in both of these disciplines.

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