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A Compiler Integrated Assistance for Optimum Data Allocation in Banked Memory Embedded Processors
"... Bank switching in embedded processors having partitioned memory architecture results in code size as well as run time overhead. An algorithm and its application to assist the compiler in eliminating the redundant bank switching codes introduced and deciding the optimum data allocation to banked memo ..."
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Bank switching in embedded processors having partitioned memory architecture results in code size as well as run time overhead. An algorithm and its application to assist the compiler in eliminating the redundant bank switching codes introduced and deciding the optimum data allocation to banked memory is presented in this work. A relation matrix formed for the memory bank state transition corresponding to each bank selection instruction is used for the detection of redundant codes. Data allocation to memory is done by considering all possible permutation of memory banks and combination of data. The compiler output corresponding to each data mapping scheme is subjected to a static machine code analysis which identifies the one with minimum number of bank switching codes. Even though the method is compiler independent, the algorithm utilizes certain architectural features of the target processor. A prototype based on PIC 16F87X microcontrollers is described. This method scales well into larger number of memory blocks and other architectures so that high performance compilers can integrate this technique for efficient code generation. The technique is illustrated with an example.
Compilation and Simulation Tool Chain for Memory Aware Energy Optimizations
"... Abstract. Memory hierarchies are known to be the energy bottleneck of portable embedded devices. Numerous memory aware energy optimizations have been proposed. However, both the optimization and the validation is performed in an ad-hoc manner as a coherent compilation and simulation framework does n ..."
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Abstract. Memory hierarchies are known to be the energy bottleneck of portable embedded devices. Numerous memory aware energy optimizations have been proposed. However, both the optimization and the validation is performed in an ad-hoc manner as a coherent compilation and simulation framework does not exist as yet. In this paper, we present such a framework for performing memory hierarchy aware energy optimization. Both the compiler and the simulator are configured from a single memory hierarchy description. Significant savings of upto 50 % in the total energy dissipation are reported. 1
10th International Workshop on Software & Compilers for Embedded Systems (SCOPES) 2007 Operating system integrated energy aware scratchpad allocation strategies for multiprocess applications ∗
"... Various scratchpad allocation strategies have been developed in the past. Most of them target the reduction of energy consumption. These approaches share the necessity of having direct access to the scratchpad memory. In earlier embedded systems this was always true, but with the increasing complexi ..."
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Various scratchpad allocation strategies have been developed in the past. Most of them target the reduction of energy consumption. These approaches share the necessity of having direct access to the scratchpad memory. In earlier embedded systems this was always true, but with the increasing complexity of tasks systems have to perform, an additional operating system layer between the hardware and the application is becoming mandatory. This paper presents an approach to integrate a scratchpad memory manager into the operating system. The goal is to minimize energy consumption. In contrast to previous work, compile time knowledge about the application’s behavior is taken into account. A set of fast heuristic allocation methods is proposed in this paper. An in-depth study and comparison of achieved energy savings and cycle reductions was performed. The results show that even in the highly dynamic environment of an operating system equipped embedded system, up to 83 % energy consumption reduction can be achieved. 1
GENETIC HEURISTICS FOR REDUCING MEMORY ENERGY CONSUMPTION IN EMBEDDED SYSTEMS
"... Abstract: Nowadays, reducing memory energy has become one of the top priorities of many embedded systems design-ers. Given the power, cost, performance and real-time advantages of Scratch-Pad Memories (SPMs), it is not surprising that SPM is becoming a common form of SRAM in embedded processors toda ..."
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Abstract: Nowadays, reducing memory energy has become one of the top priorities of many embedded systems design-ers. Given the power, cost, performance and real-time advantages of Scratch-Pad Memories (SPMs), it is not surprising that SPM is becoming a common form of SRAM in embedded processors today. In this paper, we focus on heuristic methods for SPMs careful management in order to reduce memory energy consumption. We propose Genetic Heuristics for memory management which are, to the best of our knowledge, new origi-nal alternatives to the best known existing heuristic (BEH). Our Genetic Heuristics outperform BEH. In fact, experimentations performed on our benchmarks show that our Genetic Heuristics consume from 76.23 % up to 98.92 % less energy than BEH in different configurations. In addition they are easy to implement and do not require list sorting (contrary to BEH). 1
A Novel Operating System on Chip with Information Security Support for Embedded
"... Abstract—Embedded system has made great advance with the progress of semiconductor technology. System-on-chip (SOC) has provided more powerful functions for embedded systems. Scratchpad memory (SPM), which is software-controlled on-chip memory, is used in embedded systems to reduce the speed gap bet ..."
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Abstract—Embedded system has made great advance with the progress of semiconductor technology. System-on-chip (SOC) has provided more powerful functions for embedded systems. Scratchpad memory (SPM), which is software-controlled on-chip memory, is used in embedded systems to reduce the speed gap between the processors and the memory and the power consumption of memory. The architecture of embedded software will also have corresponding changes according to the latest hardware. ChipOS, a novel operating system on chip with information security support for embedded system, is proposed in this paper. It has a microkernel residing in SPM. This microkernel can execute absolutely. And it can also encapsulate the processor resources and provide virtual resources to general operating system (GPOS). At the same time, ChipOS can provide information security service through the encapsulation. The experimental results show that ChipOS has better response time and lower power consumption compared with GPOS and the security framework of ChipOS will protect GPOS with flexibility. Index Terms—scratchpad memory, operating system, information security, power-efficient, system-on-chip, embedded system I.
Stack Frames Placement in Scratch-Pad Memory for Energy Reduction of Multi-task Applications∗
"... Scratch-pad memories (SPM) are small on-chip mem-ory devices whose access is much faster and consumes much less energy than off-chip memories. While SPM are usually too small for containing all the code or data of an application, significant energy consumption re-ductions can be achieved by assignin ..."
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Scratch-pad memories (SPM) are small on-chip mem-ory devices whose access is much faster and consumes much less energy than off-chip memories. While SPM are usually too small for containing all the code or data of an application, significant energy consumption re-ductions can be achieved by assigning to them mem-ory objects which are often accessed. The stack is one of the most frequently accessed data memory object, but its dynamic behavior makes it difficult to place into the SPM. This paper presents a simple and practical technique for placing frequently accessed parts of the stack into the SPM. The technique has been designed for multi-task environments where the SPM is shared among several tasks. Results show that the proposed technique achieves energy reductions which are compa-rable to ones obtain by other techniques supporting only single-task applications. 1
