Abstract—Reducing energy consumption of embedded systems re-quires careful memory management. It has been shown that Scratch-Pad Memories (SPMs) are low size, low cost, efficient (i.e. energy saving) data structures directly managed at the software level. In this paper, we focus on heuristic methods for SPMs management. A method is efficient if the number of accesses to SPM is as large as possible and if all available space (i.e. bits) is used. We propose a Tabu Search (TS) approach for memory management which is, to the best of our knowledge, a new original alternative to the best known existing heuristic (BEH). In fact, experimentations performed on our benchmarks show that our Tabu Search method is as efficient as BEH (in terms of energy consumption) but BEH requires a sorting which can be computationally expensive for a large amount of data. TS is easy to implement and since no sorting is necessary, unlike BEH, we save the corresponding sorting time. In addition to that, in a dynamic perspective where the maximum capacity of the SPM is not known in advance, our TS heuristic will perform better than BEH. Keywords—Energy consumption, memory allocation management, optimization, Tabu Search heuristic. I.

d' ctivity eport 2006 Table of contents

This paper surveys components that are useful to build programmable, predictable, composable, and scalable multiprocessor-system-on-a-chip (MPSoC) multimedia platforms that can deliver high performance at high power-efficiency. A design-time tool flow is proposed to exploit all forms of parallelism on such platforms. As a first proof of concept, the flow is used to parallelize a relatively simple video standard on a platform consisting of off-the-shelf components. As a second proof of concept, we present the design of a high-performance platform with state-ofthe-art components. This platform targets real-time H.264 high-definition video encoding at an estimated power consumption of 700mW.

Abstract: Nowadays, reducing memory energy has become one of the top priorities of many embedded systems design-ers. Given the power, cost, performance and real-time advantages of Scratch-Pad Memories (SPMs), it is not surprising that SPM is becoming a common form of SRAM in embedded processors today. In this paper, we focus on heuristic methods for SPMs careful management in order to reduce memory energy consumption. We propose Genetic Heuristics for memory management which are, to the best of our knowledge, new origi-nal alternatives to the best known existing heuristic (BEH). Our Genetic Heuristics outperform BEH. In fact, experimentations performed on our benchmarks show that our Genetic Heuristics consume from 76.23 % up to 98.92 % less energy than BEH in different configurations. In addition they are easy to implement and do not require list sorting (contrary to BEH). 1