This paper presents an efficient method to reduce complexities of a linear network in s-domain. The new method works on circuit matrices directly and reduces the circuit complexities by eliminating subcircuits in a hierarchical way. The resulting admittances in the reduced networks are kept as rational functions of s with reduced order. Some theoretical results are characterized for the presence of common factors coming from the suppression of subcircuits. A novel common factor removal (de-cancellation) strategy based on a graph-based hierarchical subcircuit reduction process is proposed. The resulting reduction algorithm is applicable to any linear circuits in s-domain. The stability of the reduced system is enforced by applying the Hurwitz polynomial approximation. The reduced systems can be used for fast s-domain analysis and for time domain waveform evaluation. Experimental results

This paper presents an efficient way to compute the approximate time domain signal waveforms for RLCK circuits that have nontree or tree-like structures. The new method is based on a graph based approach to drive transfer function of any linear circuits. Our contribution is the introduction of Hurwitz approximation to the truncated transfer functions to enforce the stability of reduced systems. We also extend the direct truncation of the transfer (DTT) technique, which can only work for tree-structured circuits, to deal with non-tree or tree-like RLC circuits. By combining DTT technique with graph-based method, we show that the new method is capable of analyzing non-tree or treelike structured RLCK circuits which are more accurate models of deep submicron high-speed coupled interconnects. The proposed method has been tested and validated on some coupled RLCK circuits.

We present a new methodology for fast analog circuit synthesis, based on the use of parameterized layout generators and symbolic performance models (SPMs) in the synthesis loop. Fast layout generation is achieved by using efficient parameterized procedural layout generators. Fast performance estimation is achieved by using pre-compiled SPMs, stored as efficient DDD-like structures called Element Coefficient Diagrams. Techniques have been developed to include layout geometry effects in the SPMs. The accuracy and efficiency of the parasitic inclusion technique as well as the proposed methodology have been demonstrated by comparisons to traditional synthesis methods. The proposed methodology is used for the synthesis of opamps and filters and is demonstrated to achieve effective performance closure. 1.