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A general sdomain hierarchical network reduction algorithm
 in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2003
, 2003
"... This paper presents an efficient method to reduce complexities of a linear network in sdomain. The new method works on circuit matrices directly and reduces the circuit complexities by eliminating subcircuits in a hierarchical way. The resulting admittances in the reduced networks are kept as ratio ..."
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Cited by 8 (5 self)
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This paper presents an efficient method to reduce complexities of a linear network in sdomain. The new method works on circuit matrices directly and reduces the circuit complexities by eliminating subcircuits in a hierarchical way. The resulting admittances in the reduced networks are kept as rational functions of s with reduced order. Some theoretical results are characterized for the presence of common factors coming from the suppression of subcircuits. A novel common factor removal (decancellation) strategy based on a graphbased hierarchical subcircuit reduction process is proposed. The resulting reduction algorithm is applicable to any linear circuits in sdomain. The stability of the reduced system is enforced by applying the Hurwitz polynomial approximation. The reduced systems can be used for fast sdomain analysis and for time domain waveform evaluation. Experimental results
Efficient DDDbased term generation algorithm for analog circuit behavioral modeling
 In Pmc. IEEE DATE Conference
, 2003
"... Abstract — An efficient approach to generating symbolic product terms for behavioral modeling of large linear analog circuits is presented. The approach is based on a compact determinant decision diagram (DDD) representation of transfer functions and characteristics of analog circuits. The new algor ..."
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Cited by 6 (1 self)
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Abstract — An efficient approach to generating symbolic product terms for behavioral modeling of large linear analog circuits is presented. The approach is based on a compact determinant decision diagram (DDD) representation of transfer functions and characteristics of analog circuits. The new algorithm is based on the concept that a dominant term in a DDD graph can be found by searching the shortest path in the graph. But instead of traversing a whole DDD graph each time, we show that a shortest path can be found by just updating a small number of the newly added vertices after the first shortest path is found. Experimental results indicate that the new symbolic term generation algorithm outperforms both pure shortest path based algorithm and dynamic programming based algorithm, which is the fastest symbolic term generation algorithm published so far. I.
Hurwitz Stable Model Reduction for NonTree Structured RLCK Circuits
, 2003
"... This paper presents an efficient way to compute the approximate time domain signal waveforms for RLCK circuits that have nontree or treelike structures. The new method is based on a graph based approach to drive transfer function of any linear circuits. Our contribution is the introduction of Hurwi ..."
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Cited by 2 (2 self)
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This paper presents an efficient way to compute the approximate time domain signal waveforms for RLCK circuits that have nontree or treelike structures. The new method is based on a graph based approach to drive transfer function of any linear circuits. Our contribution is the introduction of Hurwitz approximation to the truncated transfer functions to enforce the stability of reduced systems. We also extend the direct truncation of the transfer (DTT) technique, which can only work for treestructured circuits, to deal with nontree or treelike RLC circuits. By combining DTT technique with graphbased method, we show that the new method is capable of analyzing nontree or treelike structured RLCK circuits which are more accurate models of deep submicron highspeed coupled interconnects. The proposed method has been tested and validated on some coupled RLCK circuits.
An efficient algorithm for transient and distortion analysis of mildly nonlinear analog circuits
 in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS
, 2004
"... Abstract — This paper presents an effective approach to transient and distortion analyses for mildly nonlinear analog circuits. Our method is based on Volterra functional series representation of nonlinear circuits. It computes the nonlinear responses using nonlinear current method which recursivel ..."
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Cited by 1 (1 self)
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Abstract — This paper presents an effective approach to transient and distortion analyses for mildly nonlinear analog circuits. Our method is based on Volterra functional series representation of nonlinear circuits. It computes the nonlinear responses using nonlinear current method which recursively solves a series of linear Volterra circuits to obtain linear and higherorder responses of a nonlinear circuit. The linear Volterra circuits are solved in frequency domain using an efficient graphbased technique, which can derive transfer functions of any large linear network very efficiently. The harmonic distortion can be directly obtained in the frequency domain while the transient responses are obtained via inverse Laplace transformation. The new algorithm takes advantage of the identical Volterra circuits for second and higher order response, which results in significant saving in deriving the transfer functions. Experimental results for a number of nonlinear circuits are obtained and compared with SPICE3 to validate the effectiveness of this method. I.
Exact and Heuristic Minimization of Determinant Decision Diagrams
, 2002
"... Determinant Decision Diagram (DDD) is a variant of binary decision diagrams (BDDs) for representing symbolic matrix determinants and cofactors in symbolic circuit analysis. DDDbased symbolic analysis algorithms have time and space complexities proportional to the number of DDD vertices. Inspired by ..."
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Determinant Decision Diagram (DDD) is a variant of binary decision diagrams (BDDs) for representing symbolic matrix determinants and cofactors in symbolic circuit analysis. DDDbased symbolic analysis algorithms have time and space complexities proportional to the number of DDD vertices. Inspired by the ideas of Rudell, Drechsler, et. al. on BDD minimization, we present lowerbound based exact and heuristic algorithms for reordering the DDD vertices to minimize the DDD size. Our new contributions are twofolds. First, we show how vertex signs, which are specific to DDDs, can be handled during neighboring vertex reordering. Second, we develop lower bounds tailored to the DDD structures, which are much tighter than the known lower bounds for BDDs. On a set of DDD examples from symbolic circuit analysis, experimental results have demonstrated that the proposed lowerbound based reordering algorithms can effectively reduce DDD sizes. It has also been demonstrated that sifting with lower bounds uses about 55 % less computation compared to sifting without using lower bounds, and sifting with the new lower bounds reduces the computation further by up to 10 % compared to sifting with known lower bounds for BDDs.
Behavioral Modeling of Analog Circuits by Dynamic SemiSymbolic Analysis
"... Abstract — The paper presents a novel approach to behavioral modeling of analog circuits by dynamic semisymbolic analysis, where some circuit parameters are kept as symbols and the others are given as numeric values. Our new method is based on the determinant decision diagram (DDD) representation o ..."
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Abstract — The paper presents a novel approach to behavioral modeling of analog circuits by dynamic semisymbolic analysis, where some circuit parameters are kept as symbols and the others are given as numeric values. Our new method is based on the determinant decision diagram (DDD) representation of smallsignal characteristics of linear analog circuits. The basic idea is to dynamically reorder DDD vertices such that all the DDD vertices corresponding to symbolic parameters are separated from DDD vertices for numerical parameters. In this way, DDD sizes of symbolic portion of DDD can be significantly reduced by suppressing numerical DDD nodes. Our new approach is different from the existing MTDDD based semisymbolic analysis method where reordering is done before DDD is constructed and DDDbased graph operations are still valid in the new method. The proposed dynamic ordering algorithm, which is based on swap of adjacent variables, also improves the existing DDDbased vertex sifting algorithm as no special sign rule is required after DDD vertices are swapped. Experimental results have demonstrated that the proposed dynamic semisymbolic method leads to up to 30 % symbolic DDD node reduction compared MTDDD method on real analog circuits and can be performed very efficiently. I.
Fast, LayoutInclusive Analog Circuit Synthesis using PreCompiled ParasiticAware Symbolic Performance Models
, 2004
"... We present a new methodology for fast analog circuit synthesis, based on the use of parameterized layout generators and symbolic performance models (SPMs) in the synthesis loop. Fast layout generation is achieved by using efficient parameterized procedural layout generators. Fast performance estimat ..."
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We present a new methodology for fast analog circuit synthesis, based on the use of parameterized layout generators and symbolic performance models (SPMs) in the synthesis loop. Fast layout generation is achieved by using efficient parameterized procedural layout generators. Fast performance estimation is achieved by using precompiled SPMs, stored as efficient DDDlike structures called Element Coefficient Diagrams. Techniques have been developed to include layout geometry effects in the SPMs. The accuracy and efficiency of the parasitic inclusion technique as well as the proposed methodology have been demonstrated by comparisons to traditional synthesis methods. The proposed methodology is used for the synthesis of opamps and filters and is demonstrated to achieve effective performance closure.
Efficient DDDbased Term Generation Algorithm for Analog Circuit Behavioral Modeling
"... Abstract — An efficient approach to generating symbolic product terms for behavioral modeling of large linear analog circuits is presented. The approach is based on a compact determinant decision diagram (DDD) representation of transfer functions and characteristics of analog circuits. The new algor ..."
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Abstract — An efficient approach to generating symbolic product terms for behavioral modeling of large linear analog circuits is presented. The approach is based on a compact determinant decision diagram (DDD) representation of transfer functions and characteristics of analog circuits. The new algorithm is based on the concept that a dominant term in a DDD graph can be found by searching the shortest path in the graph. But instead of traversing a whole DDD graph each time, we show that a shortest path can be found by just updating a small number of the newly added vertices after the first shortest path is found. Experimental results indicate that the new symbolic term generation algorithm outperforms both pure shortest path based algorithm and dynamic programming based algorithm, which is the fastest symbolic term generation algorithm published so far. I.
Use of Symbolic Performance Models in LayoutInclusive RF Low Noise Amplifier Synthesis
"... Abstract — In this paper we present a layoutinloop synthesis method for radiofrequency LNAs, which uses symbolic performance models (SPMs), parameterized layout generator and highfrequency extraction techniques in the synthesis loop. The primary focus of this work is on performance estimation us ..."
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Abstract — In this paper we present a layoutinloop synthesis method for radiofrequency LNAs, which uses symbolic performance models (SPMs), parameterized layout generator and highfrequency extraction techniques in the synthesis loop. The primary focus of this work is on performance estimation using efficient SPMs and development of techniques to include layout parasitics symbolically into the SPMs before the start of synthesis. SPMs for noise figure and distortion parameters are obtained using repetitive and weakly nonlinear symbolic analysis and are stored as precompiled Element Coefficient Diagrams (ECDs). Speedy layout generation is achieved by using parameterized procedural layout generators and full parasitic extraction is done by using multiple extractors. Quasistatic extraction is used to obtain the critical parasitic effects of interconnects and onchip inductors. The proposed methodology is used for the synthesis