A16mm 3 autonomous solar-powered sensor node with bidirectional optical communication for distributed sensor networks has been demonstrated. The device digitizes integrated sensor signals and transmits/receives data over a free-space optical link. The system consists of three die–a 0.25µm CMOS ASIC, a 2.6 mm 2 SOI solar cell array, and a micromachined four-quadrant corner-cube retroreflector (CCR), allowing it to be used in a one-to-many network configuration. The CMOS ASIC includes a photosensor, integrated 3 MHz oscillator, 69 pJ/bit optical receiver, and 31 pJ/sample ADC.

A successive approximation ADC targeted for use in distributed sensor networks is presented. The individual nodes in these sensor networks are very energy constrained. Typical use of the individual nodes will include long periods of idle time in a low power standby mode followed by a period of activity that may include sampling of the sensors, computation, and communication. The ADC reported here consumes only 3.1 µW, resulting in 31 pJ/8-bit sample at 1V supply with a maximum sampling rate slightly over 100 kS/s. The standby power consumption at 1 V supply is 41 pW. The µ-power consumption makes this one of the lowest power ADCs ever reported. 1.

Abstract—A Low power fully operational digital hearing aid chip is proposed and implemented. The Σ- ∆ ADC adopts the status controller to realize adaptive SNR technique without any external control. To achieve both low power consumption and high programmability, dedicated low power DSP with 6 control parameters is designed. The heterogeneous Σ- ∆ DAC reduces more power dissipation without performance degradation. The digital hearing aid system is fabricated in 0.18 µm CMOS technology, consumes less than 96 µW and has a die size of 2.8 mm x 1.1 mm. I.

The continued drive toward technology scaling in VLSI design has provided greater integration levels in silicon chips. Thanks to the reduction in minimum feature size and the corresponding decrease in power supply voltage, digital circuits have bene-fited from savings in area and power consumption. This approach presents a number of challenges in Complementary Metal-Oxide Semiconductor (CMOS) analog circuit design. As the gate oxide of transistors becomes thinner and power consumption increases, a lower supply voltage must be used, even though it results in performance degradation of analog circuits. This must be done in order to avoid silicon punch-through. In applications requiring low power consumption and moderate conversion speed, one of the most frequently used analog-to-digital converter (ADC) architec-tures is the successive approximation. As data converters are mixed-signal circuits, containing both analog and digital circuits, they suffer from the same problems just described. This thesis presents the design of a low-voltage successive approximation ADC based on a Switched Opamp comparator. The proposed comparator archi-

Abstract — We present a low-power Σ − ∆ modulator to be used in the baseband sections of wireless sensor network receivers with 0.65V Vdd operation. The design is optimized for low-power consumption and low operating supply by minimizing operational amplifier open-loop gain. Simple differential pair amplifiers with ≈ 40dB of open loop gain and low noise factor are employed as the integrator cores and guarantee a spurious-free dynamic range(SFDR) of 63dB. The prototype employs only standard Vth devices and dissipates 27µW to achieve 65dB dynamic range in a 50KHz bandwidth, including regulated bias. The peak SNDR of 59.5dB corresponds to a figure of merit (FOM) of 0.36pJ/Conv.Step. I.

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