We present results from experiments in which a genetic algorithm (GA) was used to evolve cellular automata (CAs) to perform a particular computational task—one-dimensional density classification. We look in detail at the evolutionary mechanisms producing the GA’s behavior on this task and the impediments faced by the GA. In particular, we identify four “epochs of innovation ” in which new CA strategies for solving the problem are discovered by the GA, describe how these strategies are implemented in CA rule tables, and identify the GA mechanisms underlying their discovery. The epochs are characterized by a breaking of the task’s symmetries on the part of the GA. The symmetry breaking results in a short-term fitness gain but ultimately prevents the discovery of the most highly fit strategies. We discuss the extent to which symmetry breaking and other impediments are general phenomena in any GA search. 1.

VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasis on standard ce11and macro

s: Jan. 1992 -- Dec. 1994 ffl CTI: Current Technology Index Jan./Feb. 1993 -- Jan./Feb. 1994 ffl DAI: Dissertation Abstracts International: Vol. 53 No. 1 -- Vol. 55 No. 4 (1994) ffl EEA: Electrical & Electronics Abstracts: Jan. 1991 -- Dec. 1994 ffl P: Index to Scientific & Technical Proceedings: Jan. 1986 -- Feb. 1995 (except Nov. 1994) ffl EI A: The Engineering Index Annual: 1987 -- 1992 ffl EI M: The Engineering Index Monthly: Jan. 1993 -- Dec. 1994 The following GA researchers have already kindly supplied their complete autobibliographies and/or proofread references to their papers: Dan Adler, Patrick Argos, Jarmo T. Alander, James E. Baker, Wolfgang Banzhaf, Ralf Bruns, I. L. Bukatova, Thomas Back, Yuval Davidor, Dipankar Dasgupta, Marco Dorigo, Bogdan Filipic, Terence C. Fogarty, David B. Fogel, Toshio Fukuda, Hugo de Garis, Robert C. Glen, David E. Goldberg, Martina Gorges-Schleuter, Jeffrey Horn, Aristides T. Hatjimihail, Mark J. Jakiela, Richard S. Judson, Akihiko Konaga...

Given a parallel program represented by a task graph, the objective of a scheduling algorithm is to minimize the overall execution time of the program by properly assigning the nodes of the graph to the processors. This multiprocessor scheduling problem is NP-complete even with simplifying assumptions, and becomes more complex under relaxed assumptions such as arbitrary precedence constraints, and arbitrary task execution and communication times. The present literature on this topic is a large repertoire of heuristics that produce good solutions in a reasonable amount of time. These heuristics, however, have restricted applicability in a practical environment because they have a number of fundamental problems including high time complexity, lack of scalability, and no performance guarantee with respect to optimal solutions. Recently, genetic algorithms (GAs) have been widely reckoned as a useful vehicle for obtaining high quality or even optimal solutions for a broad range of combinato...

Automatic graphic object layout methods have long been studied in many application areas in which graphic objects should be laid out to satisfy the constraints specific to each application. In those areas, carefully designed layout algorithms should be used to satisfy each application's constraints. However, those algorithms tend to be complicated and not reusable for other applications. Moreover, it is difficult to add each user's preferences to the layout scheme of the algorithm. To overcome these difficulties, we developed a general-purpose interactive graphic layout system GALAPAGOS based on genetic algorithms. GALAPAGOS is general-purpose because graphic objects are laid out not by specifying how to lay them out, but just by specifying the preferences for the layout. GALAPAGOS can not only lay out complicated graphs automatically, but also allow users to modify the constraints at run time so that users can tell the system their own preferences.

This paper presents an integrated approach to hardware software partitioning and hardware design space exploration. We propose a genetic algorithm which performs hardware software partitioning on a task graph while simultaneously contemplating various design alternatives for tasks mapped to hardware. We primarily deal with data dominated designs typically found in digital signal processing and image processing applications. A detailed description of various genetic operators is presented. We provide results to illustrate the effectiveness of our integrated methodology.

We propose a new evolutionary method of extracting user preferences from examples shown to an automatic graph layout system. Using stochastic methods such as simulated annealing and genetic algorithms, automatic layout systems can find a good layout using an evaluation function which can calculate how good a given layout is. However, the evaluation function is usually not known beforehand, and it might vary from user to user. In our system, users show the system several pairs of good and bad layout examples, and the system infers the evaluation function from the examples using genetic programming technique. After the evaluation function evolves to reflect the preferences of the user, it is used as a general evaluation function for laying out graphs. The same technique can be used for a wide range of adaptive user interface systems.

This paper presents an unified approach for partitioning and synthesizing high-level design specifications onto dynamically reconfigurable multi-fpga architectures. We use the Joint Photographic Experts Group (jpeg) still image compression algorithm as a design example to demonstrate the effectiveness of our approach. Central to our approach is the sparcs (Synthesis and Partitioning for Adaptive Reconfigurable Computing System) design environment that consists of a tightly integrated collection of synthesis and partitioning tools, which can generate multiple temporal configurations of a design for any multi-fpga board architecture. We present the design flow through the sparcs system, consisting of temporal partitioning, spatial partitioning and design synthesis. We have compared two versions of the jpeg compression algorithm, one with the fpga board configured once (static) and the other with multiple reconfigurations (dynamic) . The multiple board configurations for the design examp...

In this paper, we present a methodology for rapid prototyping of linear time-invariant analog systems. The prototyping hardware is composed of field-programmable analog arrays (FPAAs) to enable rapid evaluation and validation of analog designs. Starting with a signal flow graph description of the system, a library-based technology mapping phase produces FPAA designs optimized for area. The technology mapper then explores the design space by performing gain distribution. Technology mapping is followed by the placement and routing phase that generates the physical layout on the target single-segment array-based FPAA architecture. We employ an integrated place and route approach in order to guarantee routability and performance. 1. Introduction The VHDL-AMS Synthesis Environment (VASE) being developed at the University of Cincinnati performs synthesis of analog designs from specifications in VHDLAMS [1]. Rapid prototyping of these designs using fieldprogrammable analog arrays (FPAAs) en...

This technical report is prepared to record the preliminary work carried out in beginning a research project on the solution of a group of related problems by means of Genetic Algorithms (GA's). These problems include integrated circuit layout compaction, bin packing, and nesting. The principal problem is compaction, with the others serving to illuminate and guide the compaction work, as well as possibly receiving benefits from new tools developed. Efficient and near-optimal solution of the compaction problem will enhance the linkage between symbolic level modeling of the layout and the mask level design of hierarchical (fragment-based), ultra-fast, lowpower analog and logic circuits. The research goals are to develop new methodologies, abstractions, and theory that lead to more efficiently defined and utilized Computer-Aided Design (CAD) algorithms and tools for compaction, bin packing and nesting. These new methodologies will incorporate important improvements in the handling of the physical, technological, and optimization aspects of compaction. More effective solution of the bin packing and nesting problems can help to solve the compaction problem, as well as being valuable in their own right for many practical problems. This will be accomplished by defining a new approach to the use of Genetic Algorithms (GAs)--for the compaction, bin packing, and nesting problems. The research will concentrate mostly on the application area of high-speed, low-power analog and digital circuits with clock rates up to 20 GHz. In many applications in this high performance area, dramatically reduced chip area and signal delays are important design requirements. The technology area of interest is multi-chip modules (MCM) based on current or advanced silicon and GaAs technologies [1]. Th...