Results 1  10
of
10
Multicore curvebased cryptoprocessor with reconfigurable modular arithmetic logic units over GF(2 n
 IEEE Transactions on Computers
"... Abstract—This paper presents a reconfigurable curvebased cryptoprocessor that accelerates scalar multiplication of Elliptic Curve Cryptography (ECC) and HyperElliptic Curve Cryptography (HECC) of genus 2 over GFð2nÞ. By allocating copies of processing cores that embed reconfigurable Modular Arithme ..."
Abstract

Cited by 11 (4 self)
 Add to MetaCart
(Show Context)
Abstract—This paper presents a reconfigurable curvebased cryptoprocessor that accelerates scalar multiplication of Elliptic Curve Cryptography (ECC) and HyperElliptic Curve Cryptography (HECC) of genus 2 over GFð2nÞ. By allocating copies of processing cores that embed reconfigurable Modular Arithmetic Logic Units (MALUs) over GFð2nÞ, the scalar multiplication of ECC/HECC can be accelerated by exploiting InstructionLevel Parallelism (ILP). The supported field size can be arbitrary up to ðn þ 1Þ 1. The superscaling feature is facilitated by defining a single instruction that can be used for all field operations and point/divisor operations. In addition, the cryptoprocessor is fully programmable and it can handle various curve parameters and arbitrary irreducible polynomials. The cost, performance, and security tradeoffs are thoroughly discussed for different hardware configurations and software programs. The synthesis results with a 0:13 m CMOS technology show that the proposed reconfigurable cryptoprocessor runs at 292 MHz, whereas the field sizes can be supported up to 587 bits. The compact and fastest configuration of our design is also synthesized with a fixed field size and irreducible polynomial. The results show that the scalar multiplication of ECC over GFð2163Þ and HECC over GFð283Þ can be performed in 29 and 63 s, respectively. Index Terms—Multiprocessor systems, processor architectures, reconfigurable hardware, arithmetic and logic units, public key cryptosystems. Ç 1
Programmable and parallel ecc coprocessor architecture: Tradeoffs between area, speed and security
 In Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES’09
, 2009
"... Abstract. Elliptic Curve Cryptography implementations are known to be vulnerable to various sidechannel attacks and fault injection attacks, and many countermeasures have been proposed. However, selecting and integrating a set of countermeasures targeting multiple attacks into an ECC design is far ..."
Abstract

Cited by 4 (2 self)
 Add to MetaCart
(Show Context)
Abstract. Elliptic Curve Cryptography implementations are known to be vulnerable to various sidechannel attacks and fault injection attacks, and many countermeasures have been proposed. However, selecting and integrating a set of countermeasures targeting multiple attacks into an ECC design is far from trivial. Security, performance and cost need to be considered together. In this paper, we describe a generic ECC coprocessor architecture, which is scalable and programmable. We demonstrate the coprocessor architecture with a set of countermeasures to address a collection of sidechannel attacks and fault attacks. The programmable design of the coprocessor enables tradeoffs between area, speed, and security. 1
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA based SoC Platform
, 2009
"... Abstract. Most hardware/software codesigns of Elliptic Curve Cryptography only have one central control unit, typically a 32 bit or 8 bit processor core. With the ability of integrating several soft processor cores into one FPGA fabric, we can have a hierarchy of controllers in one SoC design. Comp ..."
Abstract

Cited by 3 (2 self)
 Add to MetaCart
(Show Context)
Abstract. Most hardware/software codesigns of Elliptic Curve Cryptography only have one central control unit, typically a 32 bit or 8 bit processor core. With the ability of integrating several soft processor cores into one FPGA fabric, we can have a hierarchy of controllers in one SoC design. Compared to the previous codesigns trying to optimize the communication overhead between the central control unit and coprocessor over bus by using different bus protocols (e.g. OPB, PLB and FSL) or advanced techniques (e.g. DMA), our approach prevents overhead in bus transactions by introducing a local 8 bit microcontroller, PicoBlaze, in the coprocessor. As a result, the performance of the ECC coprocessor can be almost independent of the selection of bus protocols. To further accelerate the UniPicoBlaze based ECC SoC design, a DualPicoBlaze based architecture is proposed, which can achieve the maximum instruction rate of 1 instruction/cycle to the ECC datapath. Using design space exploration of a large number of system configurations of different architectures discussed in this paper, our proposed DualPicoBlaze based design also shows best tradeoff between area and speed. 1
Optimizing the hw/sw boundary of an ECC SoC design using control hierarchy and distributed storage
 Design, Automation and Test in Europe (DATE2009
, 2009
"... tography has been extensively studied in recent years. However, most of these designs have focused on the computational aspect of the ECC hardware, and not on the system integration into a SoC architecture. We study the impact of the communication link between CPU and coprocessor hardware for a typi ..."
Abstract

Cited by 2 (0 self)
 Add to MetaCart
(Show Context)
tography has been extensively studied in recent years. However, most of these designs have focused on the computational aspect of the ECC hardware, and not on the system integration into a SoC architecture. We study the impact of the communication link between CPU and coprocessor hardware for a typical ECC design, and demonstrate that the SoC may become performancelimited due to coprocessor data and instructiontransfers. A dual strategy is proposed to remove the bottleneck: introduction of local control as well as local storage in the coprocessor. We quantify the impact of this strategy on a prototype implementation for Field Programmable Gate Arrays (FPGA) and measured an average speedup in the resulting design of 9.4 times over the baseline ECC system, while the resulting system area increases by a factor of 1.6. The optimal areatime product improvement of our ECC coprocessor is 4.3 times compared to that of the baseline ECC coprocessor. Using design space exploration of a large number of system configurations using the latest FPGA technology and tools, we show that the optimal choice of ECC coprocessor parameters is strongly dependent on the efficiency of systemlevel communication. I.
HECC Goes Embedded: An Areaefficient Implementation of HECC
"... Abstract. In this paper we describe a high performance, areaefficient implementation of Hyperelliptic Curve Cryptosystems over GF(2 m). A compact Arithmetic Logic Unit (ALU) is proposed to perform multiplication and inversion. With this ALU, we show that divisor multiplication using affine coordina ..."
Abstract

Cited by 1 (1 self)
 Add to MetaCart
(Show Context)
Abstract. In this paper we describe a high performance, areaefficient implementation of Hyperelliptic Curve Cryptosystems over GF(2 m). A compact Arithmetic Logic Unit (ALU) is proposed to perform multiplication and inversion. With this ALU, we show that divisor multiplication using affine coordinates can be efficiently supported. Besides, the required throughput of memory or Register File (RF) is reduced so that area of memory/RF is reduced. We choose hyperelliptic curves using the parameters h(x) = x and f(x) = x 5 + f3x 3 + x 2 + f0. The performance of this coprocessor is substantially better than all previously reported FPGAbased implementations. The coprocessor for HECC over GF(2 83)
#.c World Scienti¯c Publishing Company DOI: 10.1142/S0218126610006153 A SINGLE FORMULA AND ITS IMPLEMENTATION IN FPGA FOR ELLIPTIC CURVE POINT ADDITION USING AFFINE REPRESENTATION ¤
, 2010
"... A formula for point addition in elliptic curves using a±ne representation and its implementation in FPGA is presented. The use of this new formula in hardware implementations of scalar multiplications for elliptic curve cryptography has the main advantages of: (i) reducing area for the implementatio ..."
Abstract
 Add to MetaCart
(Show Context)
A formula for point addition in elliptic curves using a±ne representation and its implementation in FPGA is presented. The use of this new formula in hardware implementations of scalar multiplications for elliptic curve cryptography has the main advantages of: (i) reducing area for the implementations of elliptic curve point addition, and (ii) increasing the resistance to side channel attacks of the hardware implementation itself. Hardware implementation of scalar multiplication for elliptic curve cryptography using this new formulation requires low area resources while keeping high performance compared to implementations using projective coordinates, which are usually considered faster than the a±ne coordinates.
unknown title
, 2008
"... A reconfigurable and interoperable hardware architecture for elliptic curve cryptography ..."
Abstract
 Add to MetaCart
(Show Context)
A reconfigurable and interoperable hardware architecture for elliptic curve cryptography
6Optimized SystemonChip Integration of a Programmable ECC Coprocessor
"... Most hardware/software (HW/SW) codesigns of Elliptic Curve Cryptography have focused on the computational aspect of the ECC hardware, and not on the system integration into a SystemonChip (SoC) architecture. We study the impact of the communication link between CPU and coprocessor hardware for a t ..."
Abstract
 Add to MetaCart
Most hardware/software (HW/SW) codesigns of Elliptic Curve Cryptography have focused on the computational aspect of the ECC hardware, and not on the system integration into a SystemonChip (SoC) architecture. We study the impact of the communication link between CPU and coprocessor hardware for a typical ECC design, and demonstrate that the SoC may become performancelimited due to coprocessor data and instructiontransfers. A dual strategy is proposed to remove the bottleneck: introduction of control hierarchy as well as local storage. The performance of the ECC coprocessor can be almost independent of the selection of bus protocols. Besides performance, the proposed ECC coprocessor is also optimized for scalability. Using design space exploration of a large number of system configurations of different architectures, our proposed ECC coprocessor architecture enables tradeoffs between area, speed, and security.
© 2008 Elsevier Science Reprinted with permission from Elsevier. es
"... ari uire re a on o liza pr nd 1 II FP curves in publickey cryptography in 1985. Since then elliptic curve cryptography has attained considera in the cryptographic research community r the a sed for ickey actoriz yptogr with 1 at ellip system is called point multiplication. Much effort has been all ..."
Abstract
 Add to MetaCart
ari uire re a on o liza pr nd 1 II FP curves in publickey cryptography in 1985. Since then elliptic curve cryptography has attained considera in the cryptographic research community r the a sed for ickey actoriz yptogr with 1 at ellip system is called point multiplication. Much effort has been allocated in developing methods for its efficient computation because it acts as the bottleneck in elliptic curve cryptosystems. A comprehensive review can be found in [22], for example. Point multiplication is commonly known to be an operation which is hard to parallelize because of data dependencies and much of the critical path is essential. The fastest method for computing point utilized in Koblitz curve point multiplication with the existing methods [14] whereas Montgomery point multiplication can efficiently use up to four multipliers [18,13]. Hence, the more multipliers are available the smaller is the benefit of using Koblitz curves. Koblitz curves are faster than general curves even if parallel field multipliers are available, but the difference becomes smaller which makes Koblitz curves less attractive. The contributions of our paper are twofold: (1) We present a simple and efficient method for speeding up Koblitz curve computations when parallel field multipliers
Secure Design Methodology and Implementation for Embedded Publickey Cryptosystems
, 2007
"... Proefschrift voorgedragen tot het behalen van het doctoraat in de ingenieurswetenschappen door ..."
Abstract
 Add to MetaCart
(Show Context)
Proefschrift voorgedragen tot het behalen van het doctoraat in de ingenieurswetenschappen door